From patchwork Thu Dec 10 11:34:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Catalin Marinas X-Patchwork-Id: 7818291 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E95D5BEEE1 for ; Thu, 10 Dec 2015 11:37:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 105D4205B5 for ; Thu, 10 Dec 2015 11:37:07 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DBABF205B7 for ; Thu, 10 Dec 2015 11:37:05 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a6zVL-0008S5-Bf; Thu, 10 Dec 2015 11:35:23 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a6zVC-0007FR-3W for linux-arm-kernel@lists.infradead.org; Thu, 10 Dec 2015 11:35:15 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 199A749; Thu, 10 Dec 2015 03:34:28 -0800 (PST) Received: from e104818-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BC8093F4FF; Thu, 10 Dec 2015 03:34:49 -0800 (PST) Date: Thu, 10 Dec 2015 11:34:47 +0000 From: Catalin Marinas To: Ming Lei Subject: Re: [PATCH 0/2] arm64: Non-racy PTE setting in the presence of HW AF/DBM Message-ID: <20151210113446.GF26759@e104818-lin.cambridge.arm.com> References: <1449682017-23729-1-git-send-email-catalin.marinas@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151210_033514_387764_7F51FCAE X-CRM114-Status: GOOD ( 24.34 ) X-Spam-Score: -6.9 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Will Deacon , linux-arm-kernel Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Thu, Dec 10, 2015 at 11:11:26AM +0800, Ming Lei wrote: > On Thu, Dec 10, 2015 at 1:26 AM, Catalin Marinas > wrote: > > This series addresses a potentially racy default implementation of > > ptep_set_access_flags() when hardware update of the access or dirty > > states is enabled. The first patch is some clean-up in set_pte_at() to > > improve the information reporting and replace BUG with WARN. The second > > patch contains the arm64-specific ptep_set_access_flags() > > implementation. > > > > Possible racy scenarios are described in patch 2. I think this series > > could be simplified on the following assumptions: > > > > a) if the CPUs do not support HW AF/DBM or it is disabled, no other > > agent in the system will perform such updates > > > > b) if one CPU supports HW AF/DBM, all of them must do (don't mix such > > features) > > > > Point (a) means that the current code works fine and BUG_ON() is not > > necessary. > > > > Point (b) however requires a ptep_set_access_flags() similar to the x86 > > one, i.e. only do the setting if (changed && dirty), otherwise let the > > hardware handle the updates. > > > > Anyway, while patch 2 is still debatable, I'd like to merge the first > > patch in 4.4 to avoid an unnecessary BUG_ON on hardware that doesn't > > even do DBM. > > > > Catalin > > > > > > Catalin Marinas (2): > > arm64: Improve error reporting on set_pte_at() checks > > arm64: Implement ptep_set_access_flags() for hardware AF/DBM > > > > arch/arm64/include/asm/pgtable.h | 16 ++++++++--- > > arch/arm64/mm/fault.c | 57 ++++++++++++++++++++++++++++++++++++++++ > > 2 files changed, 69 insertions(+), 4 deletions(-) > > > > With the two patches, looks no BUG is triggered any more, and just > with the following warning: > > [ 98.303645] set_pte_at: racy access flag clearing: 00e80040db000b51 > -> 00e80040db000b50 > [ 98.303660] ------------[ cut here ]------------ > [ 98.303666] WARNING: at ./arch/arm64/include/asm/pgtable.h:282 > [ 98.303669] Modules linked in: > > [ 98.303679] CPU: 2 PID: 2445 Comm: stress-ng-minco Tainted: G > W 4.4.0-rc3-next-20151203+ #65 > [ 98.303683] Hardware name: AppliedMicro Mustang/Mustang, BIOS 2.0.0 > Oct 23 2015 > [ 98.303686] task: ffffffc7c0caad00 ti: ffffffc7c0d10000 task.ti: > ffffffc7c0d10000 > [ 98.303696] PC is at pmdp_invalidate+0x104/0x11c I triggered the pmdp_invalidate() warning as well last night. The change here is safe, it's just some assumptions that split_huge_page_to_list() makes. It always marks the resulting PTEs as dirty, so we don't care about the race. I added this fix-up to the first patch: diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 002dc61a4dff..88c21c6a40fd 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -276,7 +276,8 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, * hardware updates of the pte (ptep_set_access_flags safely changes * valid ptes without going through an invalid entry). */ - if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM) && pte_valid(*ptep)) { + if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM) && + pte_valid(*ptep) && pte_valid(pte)) { VM_WARN_ONCE(!pte_young(pte), "%s: racy access flag clearing: %016llx -> %016llx", __func__, pte_val(*ptep), pte_val(pte));