| Message ID | 20160201101225.GA19687@box2.japko.eu (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Feb 01, 2016 at 11:12:26AM +0100, Krzysztof Adamski wrote: > H3 has additional PIO controller similar to what we can find on A23. > It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350. > > Signed-off-by: Krzysztof Adamski <k@japko.eu> > --- > .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + > arch/arm/boot/dts/sun8i-h3.dtsi | 12 +++ Acked-by: Rob Herring <robh@kernel.org> > drivers/pinctrl/sunxi/Kconfig | 4 + > drivers/pinctrl/sunxi/Makefile | 1 + > drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c | 105 +++++++++++++++++++++ > 5 files changed, 123 insertions(+) > create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c
On Mon, Feb 1, 2016 at 6:12 PM, Krzysztof Adamski <k@japko.eu> wrote: > H3 has additional PIO controller similar to what we can find on A23. > It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350. > > Signed-off-by: Krzysztof Adamski <k@japko.eu> > --- > .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + > arch/arm/boot/dts/sun8i-h3.dtsi | 12 +++ > drivers/pinctrl/sunxi/Kconfig | 4 + > drivers/pinctrl/sunxi/Makefile | 1 + > drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c | 105 > +++++++++++++++++++++ > 5 files changed, 123 insertions(+) > create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c > > diff --git > a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt > b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt > index 9213b27..730a917 100644 > --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt > +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt > @@ -20,6 +20,7 @@ Required properties: > "allwinner,sun9i-a80-pinctrl" > "allwinner,sun9i-a80-r-pinctrl" > "allwinner,sun8i-a83t-pinctrl" > + "allwinner,sun8i-h3-r-pinctrl" > "allwinner,sun8i-h3-pinctrl" h3-r-pinctrl comes after h3-pinctrl > > - reg: Should contain the register physical address and length for the > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi > b/arch/arm/boot/dts/sun8i-h3.dtsi > index 1524130e..745f64c 100644 > --- a/arch/arm/boot/dts/sun8i-h3.dtsi > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > @@ -493,5 +493,17 @@ > interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > }; > + > + r_pio: pinctrl@01f02c00 { > + compatible = "allwinner,sun8i-h3-r-pinctrl"; > + reg = <0x01f02c00 0x400>; > + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&bus_gates 69>; This is probably wrong. According to other SoCs all R_ block peripherals have clock gates and reset controls in the PRCM. > + gpio-controller; > + #gpio-cells = <3>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + Extra new line here. Also please split this into a separate patch. > }; > }; > diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig > index f8dbc8b..75a26c9 100644 > --- a/drivers/pinctrl/sunxi/Kconfig > +++ b/drivers/pinctrl/sunxi/Kconfig > @@ -55,6 +55,10 @@ config PINCTRL_SUN8I_H3 > def_bool MACH_SUN8I > select PINCTRL_SUNXI_COMMON > > +config PINCTRL_SUN8I_H3_R > + def_bool MACH_SUN8I > + select PINCTRL_SUNXI_COMMON > + > config PINCTRL_SUN9I_A80 > def_bool MACH_SUN9I > select PINCTRL_SUNXI_COMMON > diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile > index ef82f22..a5d56f1 100644 > --- a/drivers/pinctrl/sunxi/Makefile > +++ b/drivers/pinctrl/sunxi/Makefile > @@ -14,5 +14,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += > pinctrl-sun8i-a23-r.o > obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o > obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o > obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o > +obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o > obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o > obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c > b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c > new file mode 100644 > index 0000000..6271ceb > --- /dev/null > +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c > @@ -0,0 +1,105 @@ > +/* > + * Allwinner H3 SoCs pinctrl driver. > + * > + * Copyright (C) 2016 Krzysztof Adamski <k@japko.eu> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/pinctrl/pinctrl.h> > + > +#include "pinctrl-sunxi.h" > + > +static const struct sunxi_desc_pin sun8i_h3_r_pins[] = { > + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "s_uart"), /* TX */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "s_uart"), /* RX */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "s_pwn"), Typo: s_pwm Regards ChenYu > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "s_cir_rx"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */ > +}; > + > +static const struct sunxi_pinctrl_desc sun8i_h3_r_pinctrl_data = { > + .pins = sun8i_h3_r_pins, > + .npins = ARRAY_SIZE(sun8i_h3_r_pins), > + .irq_banks = 1, > + .pin_base = PL_BASE, > +}; > + > +static int sun8i_h3_r_pinctrl_probe(struct platform_device *pdev) > +{ > + return sunxi_pinctrl_init(pdev, > + &sun8i_h3_r_pinctrl_data); > +} > + > +static const struct of_device_id sun8i_h3_r_pinctrl_match[] = { > + { .compatible = "allwinner,sun8i-h3-r-pinctrl", }, > + {} > +}; > + > +static struct platform_driver sun8i_h3_r_pinctrl_driver = { > + .probe = sun8i_h3_r_pinctrl_probe, > + .driver = { > + .name = "sun8i-h3-r-pinctrl", > + .of_match_table = sun8i_h3_r_pinctrl_match, > + }, > +}; > +builtin_platform_driver(sun8i_h3_r_pinctrl_driver); > -- > 2.4.2 >
On Tue, Feb 02, 2016 at 02:25:18PM +0800, Chen-Yu Tsai wrote: >On Mon, Feb 1, 2016 at 6:12 PM, Krzysztof Adamski <k@japko.eu> wrote: >> - reg: Should contain the register physical address and length for >> the >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi >> b/arch/arm/boot/dts/sun8i-h3.dtsi >> index 1524130e..745f64c 100644 >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi >> @@ -493,5 +493,17 @@ >> interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, >> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; >> }; >> + >> + r_pio: pinctrl@01f02c00 { >> + compatible = "allwinner,sun8i-h3-r-pinctrl"; >> + reg = <0x01f02c00 0x400>; >> + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&bus_gates 69>; > >This is probably wrong. According to other SoCs all R_ block peripherals >have clock gates and reset controls in the PRCM. This is problematic. I can find information about reset and gates control for this peripheral on other SoCs user manuals but there is nothing about it in H3 User Manual (https://www.dropbox.com/s/nkr9slo1o9x6i1z/Allwinner_H3_Datasheet_V1.1.pdf?dl=0). Similarly, while I think I can find r_pio clock setup for A33: https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c I can't find it for H3, though: https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw7.c Well, apart from this strange snippet: // binder r-pio CPUS_APB0_GATE to pio-clk's gate-reset-register clk = clk_get(NULL,"pio"); if(!clk || IS_ERR(clk)) printk("Error not get clk pio\n"); else { struct clk_hw *hw = __clk_get_hw(clk); struct sunxi_clk_periph *periph = to_clk_periph(hw); struct sunxi_clk_periph_gate *gate = &periph->gate; gate->reset = sunxi_clk_cpus_base+CPUS_APB0_GATE ; gate->rst_shift = 0; clk_put(clk); } Which I have to admit I don't fully understand. This seems to be setting reset line for first pio, not for r_pio - something we don't have right now. Or am I wrong here? I'm new to Allwinner SoCs, any help from veterans? Also, if that proves anything, I did test this code on OrangePi PC and PL ports works so their clock is enabled, for sure. Best regards, Krzysztof Adamski
On Tue, Feb 02, 2016 at 10:24:51AM +0100, Krzysztof Adamski wrote: >On Tue, Feb 02, 2016 at 02:25:18PM +0800, Chen-Yu Tsai wrote: >>On Mon, Feb 1, 2016 at 6:12 PM, Krzysztof Adamski <k@japko.eu> wrote: >>>- reg: Should contain the register physical address and length for >>>the >>>diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi >>>b/arch/arm/boot/dts/sun8i-h3.dtsi >>>index 1524130e..745f64c 100644 >>>--- a/arch/arm/boot/dts/sun8i-h3.dtsi >>>+++ b/arch/arm/boot/dts/sun8i-h3.dtsi >>>@@ -493,5 +493,17 @@ >>> interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, >>> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; >>> }; >>>+ >>>+ r_pio: pinctrl@01f02c00 { >>>+ compatible = "allwinner,sun8i-h3-r-pinctrl"; >>>+ reg = <0x01f02c00 0x400>; >>>+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; >>>+ clocks = <&bus_gates 69>; >> >>This is probably wrong. According to other SoCs all R_ block peripherals >>have clock gates and reset controls in the PRCM. > >This is problematic. I can find information about reset and gates control for >this peripheral on other SoCs user manuals but there is nothing about it in H3 >User Manual >(https://www.dropbox.com/s/nkr9slo1o9x6i1z/Allwinner_H3_Datasheet_V1.1.pdf?dl=0). > >Similarly, while I think I can find r_pio clock setup for A33: >https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c > >I can't find it for H3, though: >https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw7.c > >Well, apart from this strange snippet: > >// binder r-pio CPUS_APB0_GATE to pio-clk's gate-reset-register > clk = clk_get(NULL,"pio"); > if(!clk || IS_ERR(clk)) > printk("Error not get clk pio\n"); > else > { > struct clk_hw *hw = __clk_get_hw(clk); > struct sunxi_clk_periph *periph = to_clk_periph(hw); > struct sunxi_clk_periph_gate *gate = &periph->gate; > gate->reset = sunxi_clk_cpus_base+CPUS_APB0_GATE ; > gate->rst_shift = 0; > clk_put(clk); > } > > >Which I have to admit I don't fully understand. This seems to be setting reset >line for first pio, not for r_pio - something we don't have right now. Or am I >wrong here? > >I'm new to Allwinner SoCs, any help from veterans? > >Also, if that proves anything, I did test this code on OrangePi PC and PL ports >works so their clock is enabled, for sure. I did some tests and indeed, when I disabled PIO clock (bus_gates 69), R_PIO was still working while PIO did not. So I tryied to take the same address other SoCs are using (0x01f01468 - CPUS_APB0 register) and clearing 1st bit (which is enabled by default) disables R_PIO. So, well, it seems that this works the same as on other sunxi SoCs. I'll try doing proper change. Best regards, Krzysztof Adamski
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index 9213b27..730a917 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -20,6 +20,7 @@ Required properties: "allwinner,sun9i-a80-pinctrl" "allwinner,sun9i-a80-r-pinctrl" "allwinner,sun8i-a83t-pinctrl" + "allwinner,sun8i-h3-r-pinctrl" "allwinner,sun8i-h3-pinctrl" - reg: Should contain the register physical address and length for the diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 1524130e..745f64c 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -493,5 +493,17 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; + + r_pio: pinctrl@01f02c00 { + compatible = "allwinner,sun8i-h3-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 69>; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index f8dbc8b..75a26c9 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -55,6 +55,10 @@ config PINCTRL_SUN8I_H3 def_bool MACH_SUN8I select PINCTRL_SUNXI_COMMON +config PINCTRL_SUN8I_H3_R + def_bool MACH_SUN8I + select PINCTRL_SUNXI_COMMON + config PINCTRL_SUN9I_A80 def_bool MACH_SUN9I select PINCTRL_SUNXI_COMMON diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index ef82f22..a5d56f1 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -14,5 +14,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o +obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c new file mode 100644 index 0000000..6271ceb --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c @@ -0,0 +1,105 @@ +/* + * Allwinner H3 SoCs pinctrl driver. + * + * Copyright (C) 2016 Krzysztof Adamski <k@japko.eu> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun8i_h3_r_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_uart"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_uart"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_pwn"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_cir_rx"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */ +}; + +static const struct sunxi_pinctrl_desc sun8i_h3_r_pinctrl_data = { + .pins = sun8i_h3_r_pins, + .npins = ARRAY_SIZE(sun8i_h3_r_pins), + .irq_banks = 1, + .pin_base = PL_BASE, +}; + +static int sun8i_h3_r_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun8i_h3_r_pinctrl_data); +} + +static const struct of_device_id sun8i_h3_r_pinctrl_match[] = { + { .compatible = "allwinner,sun8i-h3-r-pinctrl", }, + {} +}; + +static struct platform_driver sun8i_h3_r_pinctrl_driver = { + .probe = sun8i_h3_r_pinctrl_probe, + .driver = { + .name = "sun8i-h3-r-pinctrl", + .of_match_table = sun8i_h3_r_pinctrl_match, + }, +}; +builtin_platform_driver(sun8i_h3_r_pinctrl_driver);
H3 has additional PIO controller similar to what we can find on A23. It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350. Signed-off-by: Krzysztof Adamski <k@japko.eu> --- .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + arch/arm/boot/dts/sun8i-h3.dtsi | 12 +++ drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c | 105 +++++++++++++++++++++ 5 files changed, 123 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c