From patchwork Wed Feb 17 19:51:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 8342911 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4C8D3C0554 for ; Wed, 17 Feb 2016 19:54:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5AC2B20398 for ; Wed, 17 Feb 2016 19:54:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 333BA203A5 for ; Wed, 17 Feb 2016 19:54:57 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aW88j-0005QH-Qc; Wed, 17 Feb 2016 19:51:57 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aW88g-0005OP-8Q for linux-arm-kernel@lists.infradead.org; Wed, 17 Feb 2016 19:51:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EF7B23A1; Wed, 17 Feb 2016 11:50:41 -0800 (PST) Received: from e106794-lin.cambridge.arm.com (e106794-lin.cambridge.arm.com [10.1.207.63]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 156B23F246; Wed, 17 Feb 2016 11:51:30 -0800 (PST) Date: Wed, 17 Feb 2016 19:51:28 +0000 From: Jean-Philippe Brucker To: kbuild test robot Subject: Re: [arm:for-next 24/31] arch/arm/kernel/hyp-stub.S:168: Error: selected processor does not support ARM mode `ubfx r7,r7,#28,#4' Message-ID: <20160217195127.GA4566@e106794-lin.cambridge.arm.com> References: <201602180044.PcvJbrb9%fengguang.wu@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <201602180044.PcvJbrb9%fengguang.wu@intel.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160217_115154_953790_CA1FE85F X-CRM114-Status: GOOD ( 13.83 ) X-Spam-Score: -6.9 (------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier , Russell King , kbuild-all@01.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Thu, Feb 18, 2016 at 12:26:46AM +0800, kbuild test robot wrote: > tree: http://repo.or.cz/linux-2.6/linux-2.6-arm.git for-next > head: 5aeac3b523644cbc300f17d67c8fce73df9060c0 > commit: e59941b9b3817c9b1dd6662d903150fe3f3c3b0b [24/31] ARM: 8527/1: virt: enable GICv3 system registers > config: arm-allmodconfig (attached as .config) > reproduce: > wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross > chmod +x ~/bin/make.cross > git checkout e59941b9b3817c9b1dd6662d903150fe3f3c3b0b > # save the attached .config to linux build tree > make.cross ARCH=arm > > All errors (new ones prefixed by >>): > > arch/arm/kernel/hyp-stub.S: Assembler messages: > >> arch/arm/kernel/hyp-stub.S:168: Error: selected processor does not support ARM mode `ubfx r7,r7,#28,#4' > >> arch/arm/kernel/hyp-stub.S:176: Error: selected processor does not support ARM mode `isb' Selected processor being arm1136j-s, it doesn't make sense to build hyp-stub.S at all, in my opinion. We should select ARM_VIRT_EXT only when CPU_32v6 and lower are deselected (as with LPAE). I realize such a change might be too invasive for a fix, so I attached a version of my patch that builds for older architectures. If there is no objection, it will supersede the previous one. Thanks, Jean-Philippe --- From 2e188d870dcfeff0db5098d9c6ad3eaa139a7ddd Mon Sep 17 00:00:00 2001 From: Jean-Philippe Brucker Date: Tue, 22 Sep 2015 09:27:17 +0100 Subject: [PATCH v2] ARM: virt: enable GICv3 system registers ARMv8 introduces system registers for the Generic Interrupt Controller's CPU and virtual interfaces. When GICv3 is implemented, EL2 needs to allow the kernel to use those registers, by changing the value of ICC_HSRE. Signed-off-by: Jean-Philippe Brucker --- arch/arm/kernel/hyp-stub.S | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S index 2a55373..6c98210 100644 --- a/arch/arm/kernel/hyp-stub.S +++ b/arch/arm/kernel/hyp-stub.S @@ -17,6 +17,7 @@ */ #include +#include #include #include #include @@ -161,6 +162,29 @@ ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE 1: #endif +#ifdef CONFIG_ARM_GIC_V3 + @ Check whether GICv3 system registers are available + mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1 + lsr r7, r7, #28 + cmp r7, #1 + bne 2f + + @ Enable system register accesses + mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE + orr r7, r7, #(ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_SRE) + mcr p15, 4, r7, c12, c9, 5 @ ICC_HSRE + instr_sync + + @ SRE bit could be forced to 0 by firmware. + @ Check whether it sticks before accessing any other sysreg + mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE + tst r7, #ICC_SRE_EL2_SRE + beq 2f + mov r7, #0 + mcr p15, 4, r7, c12, c11, 0 @ ICH_HCR +2: +#endif + bx lr @ The boot CPU mode is left in r4. ENDPROC(__hyp_stub_install_secondary)