From patchwork Tue Mar 29 10:03:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell King - ARM Linux X-Patchwork-Id: 8685091 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DD99FC0553 for ; Tue, 29 Mar 2016 10:05:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A0AF7201E4 for ; Tue, 29 Mar 2016 10:05:12 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BF3972015E for ; Tue, 29 Mar 2016 10:05:10 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1akqUz-0000zk-11; Tue, 29 Mar 2016 10:03:45 +0000 Received: from pandora.arm.linux.org.uk ([2001:4d48:ad52:3201:214:fdff:fe10:1be6]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1akqUv-0000pT-3Y for linux-arm-kernel@lists.infradead.org; Tue, 29 Mar 2016 10:03:42 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=arm.linux.org.uk; s=pandora-2014; h=Sender:In-Reply-To:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date; bh=EQ1bsK9RmUgN38X8mDnrrhwx03UB6/K9CRbJMO9xWHs=; b=mZqhVMIhxZLHeChQi+OYHx3FHuHqTCQKBYDXGhv0oII//hRZIzu4B2MwkYzuN2/VEkgSmOIpry7FlUJZXN6I+pIhFAQ+FtnHWqx0xIjHIeiJTVPpFxxedcv1ZhKthQGdzzXQgnZ4Jq1BWHJd9iXrAdZCPYdVVcS/oBPxRbkpWFM=; Received: from n2100.arm.linux.org.uk ([fd8f:7570:feb6:1:214:fdff:fe10:4f86]:44425) by pandora.arm.linux.org.uk with esmtpsa (TLSv1:DHE-RSA-AES256-SHA:256) (Exim 4.82_1-5b7a7c0-XX) (envelope-from ) id 1akqUT-0001lp-Jn; Tue, 29 Mar 2016 11:03:13 +0100 Received: from linux by n2100.arm.linux.org.uk with local (Exim 4.76) (envelope-from ) id 1akqUP-0003ax-Pz; Tue, 29 Mar 2016 11:03:09 +0100 Date: Tue, 29 Mar 2016 11:03:09 +0100 From: Russell King - ARM Linux To: Masahiro Yamada Subject: Re: [PATCH 1/2] ARM: uniphier: fix up cache ops broadcast of ACTLR Message-ID: <20160329100308.GW19428@n2100.arm.linux.org.uk> References: <1459215505-18035-1-git-send-email-yamada.masahiro@socionext.com> <1459215505-18035-2-git-send-email-yamada.masahiro@socionext.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1459215505-18035-2-git-send-email-yamada.masahiro@socionext.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160329_030341_492816_9687F493 X-CRM114-Status: GOOD ( 16.97 ) X-Spam-Score: -5.3 (-----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arm@kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Tue, Mar 29, 2016 at 10:38:23AM +0900, Masahiro Yamada wrote: > The Boot ROM of the UniPhier ARMv7 SoCs sets ACTLR (Auxiliary Control > Register) to different values for different secure states: > > [1] Set ACTLR to 0x41 for Non-secure boot > [2] Set ACTLR to 0x40 for Secure boot > > [1] is okay, but [2] is a problem. Because of commit 1b3a02eb4523 > ("ARMv7: Check whether the SMP/nAMP mode was already enabled"), > if bit 6 (SMP bit) is already set, the kernel skips the ACTLR setting. > In that case, bit 0 (FW bit) is never set, so cache ops is not > broadcasted, causing a cache coherency problem. > > To solve the problem, this commit sets the bit 0 of ACTLR if the bit 4 > has already been set. This change is harmless for [1] because the > Boot ROM has already set NSACR (Non-secure Access Control Register) > bit 18 (NS_SMP bit) before switching to Non-secure state in order to > allow write access to the ACTLR. The test in proc-v7.S is too weak, we should probably tighten it to prevent these kinds of problems, iow: arch/arm/mm/proc-v7.S | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) Tested-by: Masahiro Yamada diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 0f8963a7e7d9..6fcaac8e200f 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -281,12 +281,12 @@ __v7_ca17mp_setup: bl v7_invalidate_l1 ldmia r12, {r1-r6, lr} #ifdef CONFIG_SMP + orr r10, r10, #(1 << 6) @ Enable SMP/nAMP mode ALT_SMP(mrc p15, 0, r0, c1, c0, 1) - ALT_UP(mov r0, #(1 << 6)) @ fake it for UP - tst r0, #(1 << 6) @ SMP/nAMP mode enabled? - orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode - orreq r0, r0, r10 @ Enable CPU-specific SMP bits - mcreq p15, 0, r0, c1, c0, 1 + ALT_UP(mov r0, r10) @ fake it for UP + orr r10, r10, r0 @ Set required bits + teq r10, r0 @ Were they already set? + mcrne p15, 0, r10, c1, c0, 1 @ No, update register #endif b __v7_setup_cont