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[-next] ARM: dts: sun8i: Add NFC node to Allwinner A23/A33 SoC

Message ID 20160706003352.28194-1-icenowy@aosc.xyz (mailing list archive)
State New, archived
Headers show

Commit Message

Icenowy Zheng July 6, 2016, 12:33 a.m. UTC
Add NAND Flash controller node definition to the A23/A33 SoC.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

Comments

Maxime Ripard July 6, 2016, 8:29 p.m. UTC | #1
Hi,

On Wed, Jul 06, 2016 at 08:33:52AM +0800, Icenowy Zheng wrote:
> Add NAND Flash controller node definition to the A23/A33 SoC.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

Has this ever been tested? On what board, with what NAND chip?

> ---
>  arch/arm/boot/dts/sun8i-a23-a33.dtsi | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> index 7e05e09..270c38a 100644
> --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> @@ -209,6 +209,14 @@
>  					"apb2_uart3", "apb2_uart4";
>  		};
>  
> +		nand_clk: clk@01c20080 {
> +			#clock-cells = <0>;
> +			compatible = "allwinner,sun4i-a10-mod0-clk";
> +			reg = <0x01c20080 0x4>;
> +			clocks = <&osc24M>, <&pll6 1>;
> +			clock-output-names = "nand";
> +		};
> +

This should be in a separate patch.

Thanks!
Maxime
Icenowy Zheng July 7, 2016, 12:04 a.m. UTC | #2
07.07.2016, 04:29, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> Hi,
>
> On Wed, Jul 06, 2016 at 08:33:52AM +0800, Icenowy Zheng wrote:
>>  Add NAND Flash controller node definition to the A23/A33 SoC.
>>
>>  Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>
> Has this ever been tested? On what board, with what NAND chip?
>
>>  ---
>>   arch/arm/boot/dts/sun8i-a23-a33.dtsi | 23 +++++++++++++++++++++++
>>   1 file changed, 23 insertions(+)
>>
>>  diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>>  index 7e05e09..270c38a 100644
>>  --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>>  +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>>  @@ -209,6 +209,14 @@
>>                                           "apb2_uart3", "apb2_uart4";
>>                   };
>>
>>  + nand_clk: clk@01c20080 {
>>  + #clock-cells = <0>;
>>  + compatible = "allwinner,sun4i-a10-mod0-clk";
>>  + reg = <0x01c20080 0x4>;
>>  + clocks = <&osc24M>, <&pll6 1>;
>>  + clock-output-names = "nand";
>>  + };
>>  +
>
> This should be in a separate patch.
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com

with a http://linux-sunxi.org/Aoson_M751s tablet, (SKhynix H27UCG8T2ETR-BC NAND chip).

I used the patchset at http://lists.infradead.org/pipermail/linux-mtd/2016-June/067848.html to ensure the NAND chip to work properly (otherwise the chip id cannot be correctly identified)
Maxime Ripard July 7, 2016, 7:23 a.m. UTC | #3
On Thu, Jul 07, 2016 at 08:04:41AM +0800, Icenowy Zheng wrote:
> with a http://linux-sunxi.org/Aoson_M751s tablet, (SKhynix
> H27UCG8T2ETR-BC NAND chip).
> 
> I used the patchset at
> http://lists.infradead.org/pipermail/linux-mtd/2016-June/067848.html
> to ensure the NAND chip to work properly (otherwise the chip id
> cannot be correctly identified)

(Please reply in-line and wrap your mails).

Ok. That needs to be in the commit log then.

Thanks!
Maxime
diff mbox

Patch

diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 7e05e09..270c38a 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -209,6 +209,14 @@ 
 					"apb2_uart3", "apb2_uart4";
 		};
 
+		nand_clk: clk@01c20080 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20080 0x4>;
+			clocks = <&osc24M>, <&pll6 1>;
+			clock-output-names = "nand";
+		};
+
 		mmc0_clk: clk@01c20088 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-a10-mmc-clk";
@@ -265,6 +273,21 @@ 
 			#dma-cells = <1>;
 		};
 
+		nfc: nand@01c03000 {
+			compatible = "allwinner,sun4i-a10-nand";
+			reg = <0x01c03000 0x1000>;
+			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ahb1_gates 13>, <&nand_clk>;
+			clock-names = "ahb", "mod";
+			dmas = <&dma 5>;
+			dma-names = "rxtx";
+			resets = <&ahb1_rst 13>;
+			reset-names = "ahb";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		mmc0: mmc@01c0f000 {
 			compatible = "allwinner,sun5i-a13-mmc";
 			reg = <0x01c0f000 0x1000>;