From patchwork Wed Sep 7 21:35:15 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 9320105 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8539C6077F for ; Wed, 7 Sep 2016 21:54:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 729772942B for ; Wed, 7 Sep 2016 21:54:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 65C842943F; Wed, 7 Sep 2016 21:54:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DABED2942B for ; Wed, 7 Sep 2016 21:54:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bhklx-00087e-H7; Wed, 07 Sep 2016 21:52:45 +0000 Received: from casper.infradead.org ([2001:770:15f::2]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bhkWp-00022x-Tx for linux-arm-kernel@bombadil.infradead.org; Wed, 07 Sep 2016 21:37:08 +0000 Received: from mail-pf0-x230.google.com ([2607:f8b0:400e:c00::230]) by casper.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bhkWm-0004y6-9X for linux-arm-kernel@lists.infradead.org; Wed, 07 Sep 2016 21:37:06 +0000 Received: by mail-pf0-x230.google.com with SMTP id p64so10490486pfb.1 for ; Wed, 07 Sep 2016 14:36:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=E1uCch/XDZpGF/OZLH6wXrdFktBPu8+pilt48idqXAA=; b=hPayV1UpLbUHBv9rqsPGdAM768sbmlp37V654gVrl1Q7n7+xyizjyVUhxIx7dm0Shn BnmSMWxCyYxt7FT1s6zvcPdHsF8aKSyAD7ZUBNHdd2vj/+RNu33Dw71Zsl4aMf9/MZL8 1I7UHhKTa7CaZcmCGjLbtpwOmvIPQkVcKncL0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=E1uCch/XDZpGF/OZLH6wXrdFktBPu8+pilt48idqXAA=; b=lX8wAHAaadE8SAcT/LwoHJ0RZwZBdrB8EpUBeQ8AhC+9gadQ2F0YVhdoBAUoBIgoa6 5y0QGwipBZxtXjIBWxkCG+RouXCrpIXZRFdrrb0MkXftP+hKPd4OF6N9qyXW/xWHtESI 1ndSUT1E5UuQVTp64ofbro74rWY+tkuKv0CNde/tbmdQ5+CT04UsjopjNmZR7r8XUBrx /DRWoC4yyXhryPxriml6epU+DITc7/0hKa6LvOkdr22Li81aH21JUBP4tYhCWb6fads7 bkYt6IcEhe18yOSGcoCE+zP0BHPRRz5F+dux4DUvfDo+ULWKJS9Qcd09/TzUFx2t6pUO 5miA== X-Gm-Message-State: AE9vXwMhXhTfIbZoqPUchaSe3EnIVpkTlfm09jwbThT3WAUcnJwjIw1uOjIpG7ZzOqp6EDQR X-Received: by 10.98.133.10 with SMTP id u10mr85271177pfd.134.1473284143876; Wed, 07 Sep 2016 14:35:43 -0700 (PDT) Received: from localhost.localdomain (ip68-101-172-78.sd.sd.cox.net. [68.101.172.78]) by smtp.gmail.com with ESMTPSA id 75sm51015417pfw.92.2016.09.07.14.35.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Sep 2016 14:35:43 -0700 (PDT) From: Stephen Boyd To: linux-usb@vger.kernel.org Subject: [PATCH v4 18/22] usb: chipidea: msm: Add reset controller for PHY POR bit Date: Wed, 7 Sep 2016 14:35:15 -0700 Message-Id: <20160907213519.27340-19-stephen.boyd@linaro.org> X-Mailer: git-send-email 2.9.0.rc2.8.ga28705d In-Reply-To: <20160907213519.27340-1-stephen.boyd@linaro.org> References: <20160907213519.27340-1-stephen.boyd@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160907_223704_505284_6A7024DC X-CRM114-Status: GOOD ( 25.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Felipe Balbi , Arnd Bergmann , Neil Armstrong , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Andersson , Peter Chen , Greg Kroah-Hartman , Andy Gross , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The MSM chipidea wrapper has two bits that are used to reset the first or second phy. Add support for these bits via the reset controller framework, so that phy drivers can reset their hardware at the right time during initialization. Acked-by: Peter Chen Cc: Greg Kroah-Hartman Signed-off-by: Stephen Boyd --- drivers/usb/chipidea/Kconfig | 1 + drivers/usb/chipidea/ci_hdrc_msm.c | 50 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 49 insertions(+), 2 deletions(-) diff --git a/drivers/usb/chipidea/Kconfig b/drivers/usb/chipidea/Kconfig index 19c20eaa23f2..fc96f5cdcb5c 100644 --- a/drivers/usb/chipidea/Kconfig +++ b/drivers/usb/chipidea/Kconfig @@ -2,6 +2,7 @@ config USB_CHIPIDEA tristate "ChipIdea Highspeed Dual Role Controller" depends on ((USB_EHCI_HCD && USB_GADGET) || (USB_EHCI_HCD && !USB_GADGET) || (!USB_EHCI_HCD && USB_GADGET)) && HAS_DMA select EXTCON + select RESET_CONTROLLER help Say Y here if your system has a dual role high speed USB controller based on ChipIdea silicon IP. It supports: diff --git a/drivers/usb/chipidea/ci_hdrc_msm.c b/drivers/usb/chipidea/ci_hdrc_msm.c index 2489a63d3e75..fe96df7b530c 100644 --- a/drivers/usb/chipidea/ci_hdrc_msm.c +++ b/drivers/usb/chipidea/ci_hdrc_msm.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -31,8 +32,10 @@ #define HSPHY_SESS_VLD_CTRL BIT(25) /* Vendor base starts at 0x200 beyond CI base */ +#define HS_PHY_CTRL 0x0040 #define HS_PHY_SEC_CTRL 0x0078 #define HS_PHY_DIG_CLAMP_N BIT(16) +#define HS_PHY_POR_ASSERT BIT(0) struct ci_hdrc_msm { struct platform_device *ci; @@ -40,11 +43,43 @@ struct ci_hdrc_msm { struct clk *iface_clk; struct clk *fs_clk; struct ci_hdrc_platform_data pdata; + struct reset_controller_dev rcdev; bool secondary_phy; bool hsic; void __iomem *base; }; +static int +ci_hdrc_msm_por_reset(struct reset_controller_dev *r, unsigned long id) +{ + struct ci_hdrc_msm *ci_msm = container_of(r, struct ci_hdrc_msm, rcdev); + void __iomem *addr = ci_msm->base; + u32 val; + + if (id) + addr += HS_PHY_SEC_CTRL; + else + addr += HS_PHY_CTRL; + + val = readl_relaxed(addr); + val |= HS_PHY_POR_ASSERT; + writel(val, addr); + /* + * wait for minimum 10 microseconds as suggested by manual. + * Use a slightly larger value since the exact value didn't + * work 100% of the time. + */ + udelay(12); + val &= ~HS_PHY_POR_ASSERT; + writel(val, addr); + + return 0; +} + +static const struct reset_control_ops ci_hdrc_msm_reset_ops = { + .reset = ci_hdrc_msm_por_reset, +}; + static void ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event) { struct device *dev = ci->dev->parent; @@ -186,10 +221,18 @@ static int ci_hdrc_msm_probe(struct platform_device *pdev) if (!ci->base) return -ENOMEM; - ret = clk_prepare_enable(ci->fs_clk); + ci->rcdev.owner = THIS_MODULE; + ci->rcdev.ops = &ci_hdrc_msm_reset_ops; + ci->rcdev.of_node = pdev->dev.of_node; + ci->rcdev.nr_resets = 2; + ret = reset_controller_register(&ci->rcdev); if (ret) return ret; + ret = clk_prepare_enable(ci->fs_clk); + if (ret) + goto err_fs; + reset_control_assert(reset); usleep_range(10000, 12000); reset_control_deassert(reset); @@ -198,7 +241,7 @@ static int ci_hdrc_msm_probe(struct platform_device *pdev) ret = clk_prepare_enable(ci->core_clk); if (ret) - return ret; + goto err_fs; ret = clk_prepare_enable(ci->iface_clk); if (ret) @@ -236,6 +279,8 @@ err_mux: clk_disable_unprepare(ci->iface_clk); err_iface: clk_disable_unprepare(ci->core_clk); +err_fs: + reset_controller_unregister(&ci->rcdev); return ret; } @@ -247,6 +292,7 @@ static int ci_hdrc_msm_remove(struct platform_device *pdev) ci_hdrc_remove_device(ci->ci); clk_disable_unprepare(ci->iface_clk); clk_disable_unprepare(ci->core_clk); + reset_controller_unregister(&ci->rcdev); return 0; }