| Message ID | 20160920162450.4046-1-gregory.clement@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 09/20, Gregory CLEMENT wrote: > From: Jamie Lentin <jm@lentin.co.uk> > > Referring to the u-boot sources for the Netgear WNR854T, add support > for the mv88f5181. > > [gregory.clement@free-electrons.com: fix commit title] > Signed-off-by: Jamie Lentin <jm@lentin.co.uk> > Reviewed-by: Andrew Lunn <andrew@lunn.ch> > Acked-by: Rob Herring <robh@kernel.org> > Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> > --- > > Hi Stephen and Mike, > > do you agree to give your acked-by on this patch. It is part of a > convertion of old orion5x Socv to the device tree. If you acked-by > this one, then I will be able to take it in my tree and avoiding > breaking the git bisect. Is the problem that we're changing some dts files somewhere and those platforms would stop booting if this change wasn't present? Given that we're adding a new compatible it seems like we're adding new SoC support, so having the clk patch and the dts patch come together in -next via a merge instead of basing the dts patch on top of the clk patch would be how things are normally done. If we're really changing some dts to be backwards incompatible, then I understand the bisect problem and you can have my ack. Acked-by: Stephen Boyd <sboyd@codeaurora.org.
Hi Stephen, On mar., sept. 20 2016, Stephen Boyd <sboyd@codeaurora.org> wrote: > On 09/20, Gregory CLEMENT wrote: >> From: Jamie Lentin <jm@lentin.co.uk> >> >> Referring to the u-boot sources for the Netgear WNR854T, add support >> for the mv88f5181. >> >> [gregory.clement@free-electrons.com: fix commit title] >> Signed-off-by: Jamie Lentin <jm@lentin.co.uk> >> Reviewed-by: Andrew Lunn <andrew@lunn.ch> >> Acked-by: Rob Herring <robh@kernel.org> >> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> >> --- >> >> Hi Stephen and Mike, >> >> do you agree to give your acked-by on this patch. It is part of a >> convertion of old orion5x Socv to the device tree. If you acked-by >> this one, then I will be able to take it in my tree and avoiding >> breaking the git bisect. > > Is the problem that we're changing some dts files somewhere and > those platforms would stop booting if this change wasn't present? > Given that we're adding a new compatible it seems like we're > adding new SoC support, so having the clk patch and the dts patch > come together in -next via a merge instead of basing the dts > patch on top of the clk patch would be how things are normally > done. The problem appear if the dts for the board using the clock driver is merged in Linus tree before the support in the driver. At this point the board won't be able to boot. It introduces a hole in the git bisect between the merge of the clock subsystem and the arm-soc subsystem. > > If we're really changing some dts to be backwards incompatible, > then I understand the bisect problem and you can have my ack. > > Acked-by: Stephen Boyd <sboyd@codeaurora.org. Thanks, Gregory > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project
On 09/21, Gregory CLEMENT wrote: > Hi Stephen, > > On mar., sept. 20 2016, Stephen Boyd <sboyd@codeaurora.org> wrote: > > > On 09/20, Gregory CLEMENT wrote: > >> From: Jamie Lentin <jm@lentin.co.uk> > >> > >> Referring to the u-boot sources for the Netgear WNR854T, add support > >> for the mv88f5181. > >> > >> [gregory.clement@free-electrons.com: fix commit title] > >> Signed-off-by: Jamie Lentin <jm@lentin.co.uk> > >> Reviewed-by: Andrew Lunn <andrew@lunn.ch> > >> Acked-by: Rob Herring <robh@kernel.org> > >> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> > >> --- > >> > >> Hi Stephen and Mike, > >> > >> do you agree to give your acked-by on this patch. It is part of a > >> convertion of old orion5x Socv to the device tree. If you acked-by > >> this one, then I will be able to take it in my tree and avoiding > >> breaking the git bisect. > > > > Is the problem that we're changing some dts files somewhere and > > those platforms would stop booting if this change wasn't present? > > Given that we're adding a new compatible it seems like we're > > adding new SoC support, so having the clk patch and the dts patch > > come together in -next via a merge instead of basing the dts > > patch on top of the clk patch would be how things are normally > > done. > > The problem appear if the dts for the board using the clock driver is > merged in Linus tree before the support in the driver. At this point the > board won't be able to boot. > > It introduces a hole in the git bisect between the merge of the clock > subsystem and the arm-soc subsystem. Ok so that sounds like the typical case where a new SoC/board is supported and the dts files don't do anything useful until the driver support lands. We don't usually care about bisection problems here because the board doesn't transition from 'working' to 'not working'. It only transitions from 'not working' to 'working' once the clk driver and the dts files are both present in the tree.
diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt index 670c2af3e931..eb985a633d59 100644 --- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt +++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt @@ -52,6 +52,7 @@ Required properties: "marvell,dove-core-clock" - for Dove SoC core clocks "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC + "marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC "marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC "marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC "marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC diff --git a/drivers/clk/mvebu/orion.c b/drivers/clk/mvebu/orion.c index fd129566c1ce..a6e5bee23385 100644 --- a/drivers/clk/mvebu/orion.c +++ b/drivers/clk/mvebu/orion.c @@ -21,6 +21,76 @@ static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = { }; /* + * Orion 5181 + */ + +#define SAR_MV88F5181_TCLK_FREQ 8 +#define SAR_MV88F5181_TCLK_FREQ_MASK 0x3 + +static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar) +{ + u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) & + SAR_MV88F5181_TCLK_FREQ_MASK; + if (opt == 0) + return 133333333; + else if (opt == 1) + return 150000000; + else if (opt == 2) + return 166666667; + else + return 0; +} + +#define SAR_MV88F5181_CPU_FREQ 4 +#define SAR_MV88F5181_CPU_FREQ_MASK 0xf + +static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar) +{ + u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & + SAR_MV88F5181_CPU_FREQ_MASK; + if (opt == 0) + return 333333333; + else if (opt == 1 || opt == 2) + return 400000000; + else if (opt == 3) + return 500000000; + else + return 0; +} + +static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id, + int *mult, int *div) +{ + u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & + SAR_MV88F5181_CPU_FREQ_MASK; + if (opt == 0 || opt == 1) { + *mult = 1; + *div = 2; + } else if (opt == 2 || opt == 3) { + *mult = 1; + *div = 3; + } else { + *mult = 0; + *div = 1; + } +} + +static const struct coreclk_soc_desc mv88f5181_coreclks = { + .get_tclk_freq = mv88f5181_get_tclk_freq, + .get_cpu_freq = mv88f5181_get_cpu_freq, + .get_clk_ratio = mv88f5181_get_clk_ratio, + .ratios = orion_coreclk_ratios, + .num_ratios = ARRAY_SIZE(orion_coreclk_ratios), +}; + +static void __init mv88f5181_clk_init(struct device_node *np) +{ + return mvebu_coreclk_setup(np, &mv88f5181_coreclks); +} + +CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock", mv88f5181_clk_init); + +/* * Orion 5182 */