From patchwork Tue Sep 20 20:58:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Belloni X-Patchwork-Id: 9342455 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9B42D601C2 for ; Tue, 20 Sep 2016 21:01:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 88E3A29B51 for ; Tue, 20 Sep 2016 21:01:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7B76829B54; Tue, 20 Sep 2016 21:01:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2F12229B51 for ; Tue, 20 Sep 2016 21:01:40 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bmS9N-0004fQ-A5; Tue, 20 Sep 2016 21:00:21 +0000 Received: from down.free-electrons.com ([37.187.137.238] helo=mail.free-electrons.com) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bmS85-00038m-E2 for linux-arm-kernel@lists.infradead.org; Tue, 20 Sep 2016 20:59:04 +0000 Received: by mail.free-electrons.com (Postfix, from userid 110) id 73AA71C2A; Tue, 20 Sep 2016 22:58:38 +0200 (CEST) Received: from localhost (unknown [88.191.26.124]) by mail.free-electrons.com (Postfix) with ESMTPSA id 177511FA; Tue, 20 Sep 2016 22:58:38 +0200 (CEST) From: Alexandre Belloni To: Nicolas Ferre , Boris Brezillon , Stephen Boyd Subject: [PATCH v3 2/5] clk: at91: Add sama5d4 sckc support Date: Tue, 20 Sep 2016 22:58:30 +0200 Message-Id: <20160920205833.19638-3-alexandre.belloni@free-electrons.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20160920205833.19638-1-alexandre.belloni@free-electrons.com> References: <20160920205833.19638-1-alexandre.belloni@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160920_135901_910958_CF2DE209 X-CRM114-Status: GOOD ( 15.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Turquette , Alexandre Belloni , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Starting with sama5d4, the crystal oscillator is always enabled at startup and the SCKC doesn't have an OSC32EN bit anymore. Add support for that new controller. Signed-off-by: Alexandre Belloni --- .../devicetree/bindings/clock/at91-clock.txt | 3 +- drivers/clk/at91/sckc.c | 100 +++++++++++++++++++++ 2 files changed, 102 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt index 181bc8ac4e3a..5f3ad65daf69 100644 --- a/Documentation/devicetree/bindings/clock/at91-clock.txt +++ b/Documentation/devicetree/bindings/clock/at91-clock.txt @@ -6,7 +6,8 @@ This binding uses the common clock binding[1]. Required properties: - compatible : shall be one of the following: - "atmel,at91sam9x5-sckc": + "atmel,at91sam9x5-sckc" or + "atmel,sama5d4-sckc": at91 SCKC (Slow Clock Controller) This node contains the slow clock definitions. diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index f6ed711af738..60d8225715a2 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -36,6 +36,15 @@ struct clk_slow_osc { #define to_clk_slow_osc(hw) container_of(hw, struct clk_slow_osc, hw) +struct clk_sama5d4_slow_osc { + struct clk_hw hw; + void __iomem *sckcr; + unsigned long startup_usec; + bool prepared; +}; + +#define to_clk_sama5d4_slow_osc(hw) container_of(hw, struct clk_sama5d4_slow_osc, hw) + struct clk_slow_rc_osc { struct clk_hw hw; void __iomem *sckcr; @@ -417,3 +426,94 @@ static void __init of_at91sam9x5_sckc_setup(struct device_node *np) } CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc", of_at91sam9x5_sckc_setup); + +static int clk_sama5d4_slow_osc_prepare(struct clk_hw *hw) +{ + struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(hw); + + if (osc->prepared) + return 0; + + /* + * Assume that if it has already been selected (for example by the + * bootloader), enough time has aready passed. + */ + if ((readl(osc->sckcr) & AT91_SCKC_OSCSEL)) { + osc->prepared = true; + return 0; + } + + usleep_range(osc->startup_usec, osc->startup_usec + 1); + osc->prepared = true; + + return 0; +} + +static int clk_sama5d4_slow_osc_is_prepared(struct clk_hw *hw) +{ + struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(hw); + + return osc->prepared; +} + +static const struct clk_ops sama5d4_slow_osc_ops = { + .prepare = clk_sama5d4_slow_osc_prepare, + .is_prepared = clk_sama5d4_slow_osc_is_prepared, +}; + +static void __init of_sama5d4_sckc_setup(struct device_node *np) +{ + void __iomem *regbase = of_iomap(np, 0); + struct clk_hw *hw; + struct clk_sama5d4_slow_osc *osc; + struct clk_init_data init; + const char *xtal_name; + const char *parent_names[2] = { "slow_rc_osc", "slow_osc" }; + bool bypass; + int ret; + + if (!regbase) + return; + + hw = clk_hw_register_fixed_rate_with_accuracy(NULL, parent_names[0], + NULL, 0, 32768, + 250000000); + if (IS_ERR(hw)) + return; + + xtal_name = of_clk_get_parent_name(np, 0); + + bypass = of_property_read_bool(np, "atmel,osc-bypass"); + + osc = kzalloc(sizeof(*osc), GFP_KERNEL); + if (!osc) + return; + + init.name = parent_names[1]; + init.ops = &sama5d4_slow_osc_ops; + init.parent_names = &xtal_name; + init.num_parents = 1; + init.flags = CLK_IGNORE_UNUSED; + + osc->hw.init = &init; + osc->sckcr = regbase; + osc->startup_usec = 1200000; + + if (bypass) + writel((readl(regbase) | AT91_SCKC_OSC32BYP), regbase); + + hw = &osc->hw; + ret = clk_hw_register(NULL, &osc->hw); + if (ret) { + kfree(osc); + return; + } + + hw = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, 2); + if (IS_ERR(hw)) + return; + + of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); +} +CLK_OF_DECLARE(sama5d4_clk_sckc, "atmel,sama5d4-sckc", + of_sama5d4_sckc_setup);