| Message ID | 20161018015127.16981-1-stefan@agner.ch (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Oct 17, 2016 at 06:51:27PM -0700, Stefan Agner wrote: > The global timer IRQ (PPI[0], PPI 11 in device tree terms) is a > rising edge interrupt. The ARM Cortex-A5 MPCore TRM in Chapter > 10.1.2. Interrupt types and sources says: > "Interrupt is rising-edge sensitive." > > The bits seem to be read-only, hence this missconfiguration had > no negative effect. However, with commit 992345a58e0c > ("irqchip/gic: WARN if setting the interrupt type for a PPI fails") > warnings such as this get printed: > GIC: PPI11 is secure or misconfigured > > With this change the new configuration matches the default > configuration and no warning is printed anymore. > > Signed-off-by: Stefan Agner <stefan@agner.ch> Applied, thanks.
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi index a3824e6..d7fdb2a 100644 --- a/arch/arm/boot/dts/vf500.dtsi +++ b/arch/arm/boot/dts/vf500.dtsi @@ -70,7 +70,7 @@ global_timer: timer@40002200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x40002200 0x20>; - interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; interrupt-parent = <&intc>; clocks = <&clks VF610_CLK_PLATFORM_BUS>; };
The global timer IRQ (PPI[0], PPI 11 in device tree terms) is a rising edge interrupt. The ARM Cortex-A5 MPCore TRM in Chapter 10.1.2. Interrupt types and sources says: "Interrupt is rising-edge sensitive." The bits seem to be read-only, hence this missconfiguration had no negative effect. However, with commit 992345a58e0c ("irqchip/gic: WARN if setting the interrupt type for a PPI fails") warnings such as this get printed: GIC: PPI11 is secure or misconfigured With this change the new configuration matches the default configuration and no warning is printed anymore. Signed-off-by: Stefan Agner <stefan@agner.ch> --- arch/arm/boot/dts/vf500.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)