From patchwork Wed Nov 2 13:27:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rabin Vincent X-Patchwork-Id: 9409067 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4D3A16022E for ; Wed, 2 Nov 2016 13:29:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3A1DE2A17A for ; Wed, 2 Nov 2016 13:29:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2EF642A17C; Wed, 2 Nov 2016 13:29:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8B04F2A17A for ; Wed, 2 Nov 2016 13:29:13 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1c1va1-0006G4-Mx; Wed, 02 Nov 2016 13:27:49 +0000 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1c1vZw-0006CT-UB for linux-arm-kernel@lists.infradead.org; Wed, 02 Nov 2016 13:27:45 +0000 Received: by mail-lf0-x242.google.com with SMTP id i187so983936lfe.1 for ; Wed, 02 Nov 2016 06:27:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:date:from:to:cc:subject:message-id:mime-version :content-disposition:user-agent; bh=4EALsJOgv413fwp9I6z6boDDaYnGuD8TbuKLAN8OAz4=; b=YYBoXY5w9u7XNWD8Zs+DnBEzN/bjYWxGozZhrz35W0TDcHtzzUIG+XhsN9ZbDz6Or2 LrjXEob+PzEPjGbcr1KWm8DOgFnyeE3Ji6ctioLymNqZKeTF1vrdjI7Av+kyC0iV/W3p uS1tCRUJ6zgmMnvqaAJ5fe/F6X4zatrznb+fi6BhbcROX7zjtwBVU8V1295Kpkcf1+gz mg0ZiU6AuJxn0FRfvOtT5wC6kyhbI94mP3XnKydlDpmIY+h7qzws2O0fxlCnW2UG1JQi 99YSpVwcXBPR1OxtwKOZNlwchnknmskkNLhzlMQCSHu5HAt/7DK6YoJ7/zwaikqhMfp8 E9zQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:date:from:to:cc:subject:message-id :mime-version:content-disposition:user-agent; bh=4EALsJOgv413fwp9I6z6boDDaYnGuD8TbuKLAN8OAz4=; b=XQsKSFpW7zHTf+tYiE7Cb9ow3doT6jgZKg90vVgsefq3zu8vIRkUTuR3m2+hxHzTsr 4JxrxXm0PqFpQyG6dK00lfoI/6ZjyNS+xXU73fe1JF9RVGbtUdDCVcO8f5Y/as4vWE6S zskyGGqVctVmvqzcovtDpeos5FD+0232F5yIfiQ1hO4yUROYmuFgMD+W+JWd0eQ3glb4 CvzWs3RKQKgoASWch9DfGVZV5kSiHtZPHmlypQsmedZ/8PDKko53w7Yd7RdhF2Y+GTpe i3aFilImKjUzekHsiM+nigvDzK2zGNev2sYYaBI9y3G3LdIdSOpN1+HHTA6g+4fcCra2 Mz4g== X-Gm-Message-State: ABUngvcyB/wfTsxTIeEMemQubozkc+eXe7MiXjqQpClvObIw3uBVhkgSiB0P8r0qJPZ7CA== X-Received: by 10.25.20.38 with SMTP id k38mr2010824lfi.139.1478093240350; Wed, 02 Nov 2016 06:27:20 -0700 (PDT) Received: from lnxartpec.se.axis.com (rocksteady.se.axis.com. [195.60.68.156]) by smtp.gmail.com with ESMTPSA id h31sm458831ljh.31.2016.11.02.06.27.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Nov 2016 06:27:19 -0700 (PDT) Date: Wed, 2 Nov 2016 14:27:14 +0100 From: Rabin Vincent To: linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com Subject: flush_dcache_page() in ARM vs ARM64 Message-ID: <20161102132714.GA1326@lnxartpec.se.axis.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161102_062745_214614_50F21BA5 X-CRM114-Status: GOOD ( 10.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP ARMv7-A and ARMv8-A are, as far as I can see, identical in which cache behaviours they support. The data cache has to behave as PIPT while for the instruction cache, PIPT, VIPT, and ASIC-tagged VIVT behaviours are supported. See section B3.11 of the ARMv7-A ARM and section D4.9 of the ARMv8-A ARM. Both ARMv7-A with Multiprocessing Extensions and ARMv8-A broadcast cache maintenance operations to other cores. See B2.2.5 of the ARMv7-A ARM and D7.2.57 of the ARMv8-A ARM. Both arch/arm/ (for ARMv6+) and arch/arm64/ define PG_arch_1 to be PG_dcache_clean and use it to postpone flushing from flush_dcache_page() to set_pte_at(). See arch/{arm,arm64}/mm/flush.c. However, arch/arm64/'s flush_dcache_page() is implemented like this: void flush_dcache_page(struct page *page) { if (test_bit(PG_dcache_clean, &page->flags)) clear_bit(PG_dcache_clean, &page->flags); } while arch/arm/ has this: void flush_dcache_page(struct page *page) { struct address_space *mapping; /* * The zero page is never written to, so never has any dirty * cache lines, and therefore never needs to be flushed. */ if (page == ZERO_PAGE(0)) return; mapping = page_mapping(page); if (!cache_ops_need_broadcast() && mapping && !page_mapcount(page)) clear_bit(PG_dcache_clean, &page->flags); else { __flush_dcache_page(mapping, page); if (mapping && cache_is_vivt()) __flush_dcache_aliases(mapping, page); else if (mapping) __flush_icache_all(); set_bit(PG_dcache_clean, &page->flags); } } Why does arch/arm/ flush the data cache area in flush_dcache_page() for the (!mapping || page_mapcount(page)) case even on ARMv7+ME, while arch/arm64/ doesn't for ARMv8? Why does arch/arm/ invalidate the instruction cache in flush_dcache_page() for the (mapping && page_count(page)) case even for ARMv7+ME, while arch/arm64/ doesn't for ARMv8? What would break with the following patch? diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 3cced84..f1e6190 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -327,6 +327,12 @@ void flush_dcache_page(struct page *page) if (page == ZERO_PAGE(0)) return; + if (!cache_ops_need_broadcast() && cache_is_vipt_nonaliasing()) { + if (test_bit(PG_dcache_clean, &page->flags)) + clear_bit(PG_dcache_clean, &page->flags); + return; + } + mapping = page_mapping(page); if (!cache_ops_need_broadcast() &&