From patchwork Wed Dec 7 20:00:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher Covington X-Patchwork-Id: 9465139 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E881160236 for ; Wed, 7 Dec 2016 20:02:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C46D91FE7A for ; Wed, 7 Dec 2016 20:02:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B8DAA21EEB; Wed, 7 Dec 2016 20:02:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 381511FE7A for ; Wed, 7 Dec 2016 20:02:57 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1cEiPM-0006lM-Nl; Wed, 07 Dec 2016 20:01:40 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1cEiPG-0006dH-Nw for linux-arm-kernel@lists.infradead.org; Wed, 07 Dec 2016 20:01:35 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 25CE9614A2; Wed, 7 Dec 2016 20:01:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1481140874; bh=xMT7zfnbLT0+9QDLIc1nZVuDbHADidSeexSZ/y69Jk4=; h=From:To:Subject:Date:In-Reply-To:References:From; b=GVwYMq6m1RRJGV5B9TQ4qOJG1KkvfIPEKP2g7kL0CaH569MSB7o2u7F/5s3Zuxuaq w+sWJLH3jyiqQPwim8XAZLDm8i+vEk8Es7lg4PDb0SD+PTiSM5q1LsMuPTUHuVpUkh IRig88O6HA0zmNUkmb4PfWDiJVCbpPX3gHLeExd4= Received: from illium.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: cov@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 8CA1561443; Wed, 7 Dec 2016 20:01:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1481140873; bh=xMT7zfnbLT0+9QDLIc1nZVuDbHADidSeexSZ/y69Jk4=; h=From:To:Subject:Date:In-Reply-To:References:From; b=FD1yzlAbpz6715dR+nuK9vTWuPholfbNdOZyGSRMWy5Uesaazy87csdUJadpS+IMJ qcpyKbmdc5nxLllypzJMeTY/ctvEwIal65eRoivvULlEsJGteMLyz8suN2s08lK3Hv NI4ZItoA6BDgpp+ppFhHbW/dRQiDmMJVuwxHV2Y4= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 8CA1561443 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=cov@codeaurora.org From: Christopher Covington To: Catalin Marinas , Will Deacon , Christopher Covington , Shanker Donthineni , Suzuki K Poulose , Andre Przywara , Ganapatrao Kulkarni , James Morse , Andrew Pinski , Mark Rutland , Jean-Philippe Brucker , Lorenzo Pieralisi , Geoff Levand , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] arm64: Work around Falkor erratum 1003 Date: Wed, 7 Dec 2016 15:00:26 -0500 Message-Id: <20161207200028.4420-2-cov@codeaurora.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20161207200028.4420-1-cov@codeaurora.org> References: <20161207200028.4420-1-cov@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161207_120134_872270_9EA5C1C4 X-CRM114-Status: GOOD ( 16.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shanker Donthineni On the Qualcomm Datacenter Technologies Falkor v1 CPU, memory accesses may allocate TLB entries using an incorrect ASID when TTBRx_EL1 is being updated. Changing the TTBRx_EL1[ASID] and TTBRx_EL1[BADDR] fields separately using a reserved ASID will ensure that there are no TLB entries with incorrect ASID after changing the the ASID. Pseudo code: write TTBRx_EL1[ASID] to a reserved value ISB write TTBRx_EL1[BADDR] to a desired value ISB write TTBRx_EL1[ASID] to a desired value ISB Signed-off-by: Shanker Donthineni Signed-off-by: Christopher Covington --- arch/arm64/Kconfig | 11 +++++++++++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/kernel/cpu_errata.c | 7 +++++++ arch/arm64/mm/context.c | 10 ++++++++++ arch/arm64/mm/proc.S | 21 +++++++++++++++++++++ 5 files changed, 51 insertions(+), 1 deletion(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 969ef88..1004a3d 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -474,6 +474,17 @@ config CAVIUM_ERRATUM_27456 If unsure, say Y. +config QCOM_FALKOR_ERRATUM_E1003 + bool "Falkor E1003: Incorrect translation due to ASID change" + default y + help + An incorrect translation TLBI entry may be created while + changing the ASID & translation table address together for + TTBR0_EL1. The workaround for this issue is use a reserved + ASID in cpu_do_switch_mm() before switching to target ASID. + + If unsure, say Y. + endmenu diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 87b4465..cb6a8c2 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -34,7 +34,8 @@ #define ARM64_HAS_32BIT_EL0 13 #define ARM64_HYP_OFFSET_LOW 14 #define ARM64_MISMATCHED_CACHE_LINE_SIZE 15 +#define ARM64_WORKAROUND_QCOM_FALKOR_E1003 16 -#define ARM64_NCAPS 16 +#define ARM64_NCAPS 17 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index b75e917..3789e2f 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -130,6 +130,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .def_scope = SCOPE_LOCAL_CPU, .enable = cpu_enable_trap_ctr_access, }, +#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1003 + { + .desc = "Qualcomm Falkor erratum E1003", + .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, + MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0x00, 0x00), + }, +#endif { } }; diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index efcf1f7..f8d94ff 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -87,6 +87,11 @@ static void flush_context(unsigned int cpu) /* Update the list of reserved ASIDs and the ASID bitmap. */ bitmap_clear(asid_map, 0, NUM_USER_ASIDS); + /* Reserve ASID '1' for Falkor erratum E1003 */ + if (IS_ENABLED(CONFIG_QCOM_FALKOR_ERRATUM_E1003) && + cpus_have_cap(ARM64_WORKAROUND_QCOM_FALKOR_E1003)) + __set_bit(1, asid_map); + /* * Ensure the generation bump is observed before we xchg the * active_asids. @@ -239,6 +244,11 @@ static int asids_init(void) panic("Failed to allocate bitmap for %lu ASIDs\n", NUM_USER_ASIDS); + /* Reserve ASID '1' for Falkor erratum E1003 */ + if (IS_ENABLED(CONFIG_QCOM_FALKOR_ERRATUM_E1003) && + cpus_have_cap(ARM64_WORKAROUND_QCOM_FALKOR_E1003)) + __set_bit(1, asid_map); + pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS); return 0; } diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 352c73b..b4d6508 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -134,6 +134,27 @@ ENDPROC(cpu_do_resume) ENTRY(cpu_do_switch_mm) mmid x1, x1 // get mm->context.id bfi x0, x1, #48, #16 // set the ASID +#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1003 +alternative_if_not ARM64_WORKAROUND_QCOM_FALKOR_E1003 + nop + nop + nop + nop + nop + nop + nop + nop +alternative_else + mrs x2, ttbr0_el1 // get cuurent TTBR0_EL1 + mov x3, #1 // reserved ASID + bfi x2, x3, #48, #16 // set the reserved ASID + old BADDR + msr ttbr0_el1, x2 // update TTBR0_EL1 + isb + bfi x2, x0, #0, #48 // set the desired BADDR + reserved ASID + msr ttbr0_el1, x2 // update TTBR0_EL1 + isb +alternative_endif +#endif msr ttbr0_el1, x0 // set TTBR0 isb alternative_if ARM64_WORKAROUND_CAVIUM_27456