From patchwork Tue Dec 13 15:22:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 9472603 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2C51D60476 for ; Tue, 13 Dec 2016 15:26:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1F4F82851B for ; Tue, 13 Dec 2016 15:26:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1419B2853B; Tue, 13 Dec 2016 15:26:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9FF3A2851B for ; Tue, 13 Dec 2016 15:26:42 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1cGoxB-0007GC-2R; Tue, 13 Dec 2016 15:25:17 +0000 Received: from forward6p.cmail.yandex.net ([2a02:6b8:0:1465::fe]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1cGox2-0006Vi-Hr for linux-arm-kernel@lists.infradead.org; Tue, 13 Dec 2016 15:25:11 +0000 Received: from smtp2h.mail.yandex.net (smtp2h.mail.yandex.net [84.201.187.145]) by forward6p.cmail.yandex.net (Yandex) with ESMTP id 097FA219B6; Tue, 13 Dec 2016 18:24:45 +0300 (MSK) Received: from smtp2h.mail.yandex.net (localhost.localdomain [127.0.0.1]) by smtp2h.mail.yandex.net (Yandex) with ESMTP id CBEE37819F6; Tue, 13 Dec 2016 18:24:33 +0300 (MSK) Received: by smtp2h.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id VrbkazA9aJ-OOna9oiG; Tue, 13 Dec 2016 18:24:31 +0300 (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aosc.xyz; s=mail; t=1481642672; bh=s+RXGzLxT9/w5trp28CMJ5I7pgP/YxdQVT2ah50jInA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=rmU7Q8ty6xgnA0ptY/tjX+0k9pNqjtaeBiahl76AIWuUMg0RdycAywgbdB9D2PaBi 6rJ+UVCHrD8kJc/7jo+9zJ+f//vMVoLuOT+WOUMKSy8vuYFXYAe1DZIJxdw3gA2kcc +Jg/4SBei9JRpTe/Hm5yexQVHrcZvDIXfWl6otB8= Authentication-Results: smtp2h.mail.yandex.net; dkim=pass header.i=@aosc.xyz X-Yandex-ForeignMX: GB X-Yandex-Suid-Status: 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 1130000036118848 From: Icenowy Zheng To: Russell King , Maxime Ripard , Chen-Yu Tsai , Michael Turquette , Stephen Boyd , Jorik Jonker , Hans de Goede , Quentin Schulz Subject: [PATCH 2/6] clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33 Date: Tue, 13 Dec 2016 23:22:48 +0800 Message-Id: <20161213152252.53749-3-icenowy@aosc.xyz> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20161213152252.53749-1-icenowy@aosc.xyz> References: <20161213152252.53749-1-icenowy@aosc.xyz> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161213_072509_019008_53BB4A4A X-CRM114-Status: UNSURE ( 8.62 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Icenowy Zheng , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to be changeable by changing the rate of PLL_CPUX. Add CLK_SET_RATE_PARENT flag to this clock. Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard --- drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c index 0f3e7d2dc19a..0d513d2674cb 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c @@ -170,7 +170,7 @@ static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", static const char * const cpux_parents[] = { "osc32k", "osc24M", "pll-cpux" , "pll-cpux" }; static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, - 0x050, 16, 2, CLK_IS_CRITICAL); + 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT); static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);