From patchwork Mon Dec 26 17:11:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 9488677 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2CF3E604B9 for ; Mon, 26 Dec 2016 17:15:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1A8AE20144 for ; Mon, 26 Dec 2016 17:15:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0D05426224; Mon, 26 Dec 2016 17:15:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5D38220144 for ; Mon, 26 Dec 2016 17:15:05 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1cLYqD-0007Qo-6i; Mon, 26 Dec 2016 17:13:41 +0000 Received: from forward20o.cmail.yandex.net ([37.9.109.219]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1cLYq7-0007Lk-Ri for linux-arm-kernel@lists.infradead.org; Mon, 26 Dec 2016 17:13:37 +0000 Received: from smtp3j.mail.yandex.net (smtp3j.mail.yandex.net [IPv6:2a02:6b8:0:801:1::12]) by forward20o.cmail.yandex.net (Yandex) with ESMTP id 3E41921D0A; Mon, 26 Dec 2016 20:13:10 +0300 (MSK) Received: from smtp3j.mail.yandex.net (localhost.localdomain [127.0.0.1]) by smtp3j.mail.yandex.net (Yandex) with ESMTP id DFC0162408A5; Mon, 26 Dec 2016 20:13:02 +0300 (MSK) Received: by smtp3j.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id 1AuMed9oTh-CpZqknbx; Mon, 26 Dec 2016 20:12:59 +0300 (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aosc.xyz; s=mail; t=1482772382; bh=mV6NZcNIxnapAD5tqYtsDoZH1R2xTixj9vuiI1w/fIg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=fX7Qz4GNzXlM8rYLhlfOYl3Or01IrqqFJv2rXrJZBBSmv9Y2wBxnew3TqTsUzB9g1 gxodWpnxNDgZu3w54fBy26AVKPmvK5bryZ/4ZDcuQ6JHp61MFWlrbyuv/gKzx3bBpz CmG5Ihb+UwIOdqQnBpPSH4FMMmRhssaspprAERcU= Authentication-Results: smtp3j.mail.yandex.net; dkim=pass header.i=@aosc.xyz X-Yandex-ForeignMX: US X-Yandex-Suid-Status: 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 1130000036118848 From: Icenowy Zheng To: Linus Walleij , Chen-Yu Tsai , Maxime Ripard , Rob Herring , Andre Przywara Subject: [PATCH 5/6] arm64: dts: allwinner: add Allwinner H5 .dtsi Date: Tue, 27 Dec 2016 01:11:55 +0800 Message-Id: <20161226171156.11605-2-icenowy@aosc.xyz> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20161226171156.11605-1-icenowy@aosc.xyz> References: <20161226171156.11605-1-icenowy@aosc.xyz> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161226_091336_465740_F1E2533E X-CRM114-Status: GOOD ( 15.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Andre Przywara The Allwinner H5 SoC is pin-compatible to the H3 SoC, but uses Cortex-A53 cores instead. Based on the now shared base .dtsi describing the common peripherals describe the H5 specific nodes on top of that. That symlinks in the sun8i-h3-h5.dtsi from the arch/arm tree. Signed-off-by: Andre Przywara [Icenowy: remove H5 mmc compatible (seems equal to A64), add H5 pinctrl compatible, and changes for my h3-h5 dtsi refactor, commit message change to met new arm64 naming scheme] Signed-off-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 143 +++++++++++++++++++++++++ arch/arm64/boot/dts/allwinner/sun8i-h3-h5.dtsi | 1 + 2 files changed, 144 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi create mode 120000 arch/arm64/boot/dts/allwinner/sun8i-h3-h5.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi new file mode 100644 index 000000000000..2cc372121f60 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2016 ARM Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include "sun8i-h3-h5.dtsi" + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + soc { + mmc@01c0f000 { + compatible = "allwinner,sun50i-a64-mmc", + "allwinner,sun5i-a13-mmc"; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + }; + + mmc@01c10000 { + compatible = "allwinner,sun50i-a64-mmc", + "allwinner,sun5i-a13-mmc"; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + }; + + mmc@01c11000 { + compatible = "allwinner,sun50i-a64-mmc", + "allwinner,sun5i-a13-mmc"; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + }; + + clock@01c20000 { + compatible = "allwinner,sun50i-h5-ccu", + "allwinner,sun8i-h3-ccu"; + }; + + pinctrl@01c20800 { + compatible = "allwinner,sun50i-h5-pinctrl", + "allwinner,sun8i-h3-pinctrl"; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun8i-h3-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun8i-h3-h5.dtsi new file mode 120000 index 000000000000..74f3ce9358a5 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun8i-h3-h5.dtsi @@ -0,0 +1 @@ +../../../../arm/boot/dts/sun8i-h3-h5.dtsi \ No newline at end of file