From patchwork Thu Dec 29 22:43:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher Covington X-Patchwork-Id: 9491667 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3C51860453 for ; Thu, 29 Dec 2016 22:48:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 26AA71FF15 for ; Thu, 29 Dec 2016 22:48:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 193F62018E; Thu, 29 Dec 2016 22:48:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9487E1FF15 for ; Thu, 29 Dec 2016 22:48:54 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1cMjRX-0001En-ER; Thu, 29 Dec 2016 22:45:03 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1cMjQf-0000rt-DG for linux-arm-kernel@lists.infradead.org; Thu, 29 Dec 2016 22:44:12 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 74A52614A2; Thu, 29 Dec 2016 22:43:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1483051432; bh=HzeOylZjBJPPNXRAA86xqVZIRQVo6HUqlxfLaqpJKUU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KhJLGfG3DjvvaiCeFWXgqKeycAE/GmKvLZBx225FhPkJg4xCl9qehaW/dgnFxyXj7 pJUOPmtKQYo8zecsFal6Id44lX0vg6xc69Cmz2fj2mjPNkEnuhZVmu+6jeE9R5aI5e GaF9KMqk8r0+8YGKEostur86emr4C6KZs/fgtwpE= Received: from illium.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: cov@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id D602D6145C; Thu, 29 Dec 2016 22:43:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1483051431; bh=HzeOylZjBJPPNXRAA86xqVZIRQVo6HUqlxfLaqpJKUU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D75wVwB1zMTR83cy418/8//ckHMizW8XnlGvf3hu5CKtKI3/mN6attaOjvsOxebw4 MD5LsuX64YUVBpmZI/8EIaLz2qdxzrEAqKdJKaKCqQpvccOHUFRedIW+DMUrzz02J2 GSpja28bv+fXA1eUM2+HIAzK3Hsevq4asOTEOb/s= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org D602D6145C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=cov@codeaurora.org From: Christopher Covington To: Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , Christoffer Dall , Marc Zyngier , Catalin Marinas , Will Deacon , kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, shankerd@codeaurora.org, timur@codeaurora.org, Jonathan Corbet , linux-doc@vger.kernel.org Subject: [PATCH v2 5/5] arm64: Work around Falkor erratum 1009 Date: Thu, 29 Dec 2016 17:43:35 -0500 Message-Id: <20161229224335.13531-5-cov@codeaurora.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20161229224335.13531-1-cov@codeaurora.org> References: <20161229224335.13531-1-cov@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161229_144409_678940_9A6CC609 X-CRM114-Status: GOOD ( 13.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christopher Covington MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP During a TLB invalidate sequence targeting the inner shareable domain, Falkor may prematurely complete the DSB before all loads and stores using the old translation are observed; instruction fetches are not subject to the conditions of this erratum. Signed-off-by: Christopher Covington Change-Id: I25e86b068addd68cdfba5a11142b9fc37312b1ee --- Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 10 ++++++++++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/include/asm/tlbflush.h | 5 ++++- arch/arm64/kernel/cpu_errata.c | 7 +++++++ 5 files changed, 24 insertions(+), 2 deletions(-) diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 7151aed..98bef2a 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -64,3 +64,4 @@ stable kernels. | | | | | | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | | Qualcomm | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | +| Qualcomm | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 7ce4a4b..567651b 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -495,6 +495,16 @@ config QCOM_FALKOR_E1003_RESERVED_ASID default 1 depends on QCOM_FALKOR_ERRATUM_1003 +config QCOM_FALKOR_ERRATUM_1009 + bool "Falkor E1009: Prematurely complete a DSB after a TLBI" + default y + help + Falkor CPU may prematurely complete a DSB following a TLBI xxIS + invalidate maintenance operations. Repeat the TLBI operation one + more time to fix the issue. + + If unsure, say Y. + endmenu diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 5aaf7ee..55bcd02 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -36,7 +36,8 @@ #define ARM64_MISMATCHED_CACHE_LINE_SIZE 15 #define ARM64_HAS_NO_FPSIMD 16 #define ARM64_WORKAROUND_QCOM_FALKOR_E1003 17 +#define ARM64_WORKAROUND_REPEAT_TLBI 18 -#define ARM64_NCAPS 18 +#define ARM64_NCAPS 19 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index f28813c..7313cd3 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -85,7 +85,10 @@ asm (__TLBI_INSTR(op, ##__VA_ARGS__) \ __TLBI_IO(op, ##__VA_ARGS__)); \ asm volatile ( as "\ndsb " #attr "\n" \ - : : : "memory"); } while (0) + ALTERNATIVE("nop" "\nnop" "\n", \ + __TLBI_INSTR(op, ##__VA_ARGS__) "\ndsb " #attr "\n", \ + ARM64_WORKAROUND_REPEAT_TLBI) \ + __TLBI_IO(op, ##__VA_ARGS__) : "memory"); } while (0) #define __tlbi_dsb(...) __tlbi_asm_dsb("", ##__VA_ARGS__) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 787b542..e644364 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -137,6 +137,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0x00, 0x00), }, #endif +#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 + { + .desc = "Qualcomm Falkor erratum 1009", + .capability = ARM64_WORKAROUND_REPEAT_TLBI, + MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0x00, 0x00), + }, +#endif { } };