| Message ID | 20170106065947.30631-2-wenyou.yang@atmel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi, On 06/01/2017 at 14:59:45 +0800, Wenyou Yang wrote : > For the SoCs such as SAMA5D2 and SAMA5D4 which have L2 cache, > flush the L2 cache first before entering the cpu idle. > > Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> > --- > > arch/arm/mach-at91/pm.c | 19 +++++++++++++++++++ > drivers/memory/atmel-sdramc.c | 1 + > 2 files changed, 20 insertions(+) > > diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c > index b4332b727e9c..1a60dede1a01 100644 > --- a/arch/arm/mach-at91/pm.c > +++ b/arch/arm/mach-at91/pm.c > @@ -289,6 +289,24 @@ static void at91_ddr_standby(void) > at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); > } > > +static void at91_ddr_cache_standby(void) > +{ > + u32 saved_lpr; > + > + flush_cache_all(); > + outer_disable(); > + > + saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR); > + at91_ramc_write(0, AT91_DDRSDRC_LPR, (saved_lpr & > + (~AT91_DDRSDRC_LPCB)) | AT91_DDRSDRC_LPCB_SELF_REFRESH); > + > + cpu_do_idle(); > + > + at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr); > + > + outer_resume(); > +} > + Seems good to me. Did you measure the added latency on sama5d3 if you add the cache operations in at91_ddr_standby instead of having a new function?
Hi Alexandre, > -----Original Message----- > From: Alexandre Belloni [mailto:alexandre.belloni@free-electrons.com] > Sent: 2017年1月6日 17:05 > To: Wenyou Yang - A41535 <Wenyou.Yang@microchip.com> > Cc: Russell King <linux@arm.linux.org.uk>; Nicolas Ferre > <nicolas.ferre@atmel.com>; Rob Herring <robh+dt@kernel.org>; Mark Rutland > <mark.rutland@arm.com>; linux-kernel@vger.kernel.org; Wenyou Yang - A41535 > <Wenyou.Yang@microchip.com>; devicetree@vger.kernel.org; linux-arm- > kernel@lists.infradead.org > Subject: Re: [PATCH 1/3] ARM: at91: flush the L2 cache before entering cpu idle > > Hi, > > On 06/01/2017 at 14:59:45 +0800, Wenyou Yang wrote : > > For the SoCs such as SAMA5D2 and SAMA5D4 which have L2 cache, flush > > the L2 cache first before entering the cpu idle. > > > > Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> > > --- > > > > arch/arm/mach-at91/pm.c | 19 +++++++++++++++++++ > > drivers/memory/atmel-sdramc.c | 1 + > > 2 files changed, 20 insertions(+) > > > > diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index > > b4332b727e9c..1a60dede1a01 100644 > > --- a/arch/arm/mach-at91/pm.c > > +++ b/arch/arm/mach-at91/pm.c > > @@ -289,6 +289,24 @@ static void at91_ddr_standby(void) > > at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); } > > > > +static void at91_ddr_cache_standby(void) { > > + u32 saved_lpr; > > + > > + flush_cache_all(); > > + outer_disable(); > > + > > + saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR); > > + at91_ramc_write(0, AT91_DDRSDRC_LPR, (saved_lpr & > > + (~AT91_DDRSDRC_LPCB)) | > AT91_DDRSDRC_LPCB_SELF_REFRESH); > > + > > + cpu_do_idle(); > > + > > + at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr); > > + > > + outer_resume(); > > +} > > + > > Seems good to me. Did you measure the added latency on sama5d3 if you add the > cache operations in at91_ddr_standby instead of having a new function? No, I didn't. How to measure it? Best Regards, Wenyou Yang
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index b4332b727e9c..1a60dede1a01 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -289,6 +289,24 @@ static void at91_ddr_standby(void) at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); } +static void at91_ddr_cache_standby(void) +{ + u32 saved_lpr; + + flush_cache_all(); + outer_disable(); + + saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR); + at91_ramc_write(0, AT91_DDRSDRC_LPR, (saved_lpr & + (~AT91_DDRSDRC_LPCB)) | AT91_DDRSDRC_LPCB_SELF_REFRESH); + + cpu_do_idle(); + + at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr); + + outer_resume(); +} + /* We manage both DDRAM/SDRAM controllers, we need more than one value to * remember. */ @@ -324,6 +342,7 @@ static const struct of_device_id const ramc_ids[] __initconst = { { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby }, { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby }, { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby }, + { .compatible = "atmel,sama5d4-ddramc", .data = at91_ddr_cache_standby }, { /*sentinel*/ } }; diff --git a/drivers/memory/atmel-sdramc.c b/drivers/memory/atmel-sdramc.c index b418b39af180..7e5c5c6c1348 100644 --- a/drivers/memory/atmel-sdramc.c +++ b/drivers/memory/atmel-sdramc.c @@ -48,6 +48,7 @@ static const struct of_device_id atmel_ramc_of_match[] = { { .compatible = "atmel,at91sam9260-sdramc", .data = &at91rm9200_caps, }, { .compatible = "atmel,at91sam9g45-ddramc", .data = &at91sam9g45_caps, }, { .compatible = "atmel,sama5d3-ddramc", .data = &sama5d3_caps, }, + { .compatible = "atmel,sama5d4-ddramc", .data = &sama5d3_caps, }, {}, };
For the SoCs such as SAMA5D2 and SAMA5D4 which have L2 cache, flush the L2 cache first before entering the cpu idle. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> --- arch/arm/mach-at91/pm.c | 19 +++++++++++++++++++ drivers/memory/atmel-sdramc.c | 1 + 2 files changed, 20 insertions(+)