From patchwork Sat Jan 7 20:10:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Russell King (Oracle)" X-Patchwork-Id: 9503275 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id ED3C0606E0 for ; Sat, 7 Jan 2017 20:11:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D491128413 for ; Sat, 7 Jan 2017 20:11:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C6B8428450; Sat, 7 Jan 2017 20:11:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4986F28413 for ; Sat, 7 Jan 2017 20:11:58 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cPxLG-0005mo-QV; Sat, 07 Jan 2017 20:11:54 +0000 Received: from pandora.armlinux.org.uk ([2001:4d48:ad52:3201:214:fdff:fe10:1be6]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cPxL9-0005Yt-21 for linux-arm-kernel@lists.infradead.org; Sat, 07 Jan 2017 20:11:50 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=armlinux.org.uk; s=pandora-2014; h=Sender:In-Reply-To:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date; bh=Xrp1nfFRTskpOHDfk9fwugNXAngjjCqDMwDO9+B7GUw=; b=fTMwjthp0mE6kP+5cL9y9EiWhq54lrVA9+dbGnR46dskemSBcYuP5/GJ00USSGbTT0FRv54jrWZ9aKeiB3dri4f0MZ3O5N5bkicaI5Vn9c/MgS9gblucRfZZ3MwQAxXFDoda+4i/p1ORbyPp+wJC3GtIV++uZBDCky8DZ4hZyOg=; Received: from n2100.armlinux.org.uk ([fd8f:7570:feb6:1:214:fdff:fe10:4f86]:34123) by pandora.armlinux.org.uk with esmtpsa (TLSv1:DHE-RSA-AES256-SHA:256) (Exim 4.82_1-5b7a7c0-XX) (envelope-from ) id 1cPxKO-0004cl-QC; Sat, 07 Jan 2017 20:11:01 +0000 Received: from linux by n2100.armlinux.org.uk with local (Exim 4.76) (envelope-from ) id 1cPxKL-0000N8-IA; Sat, 07 Jan 2017 20:10:57 +0000 Date: Sat, 7 Jan 2017 20:10:57 +0000 From: Russell King - ARM Linux To: Thomas Petazzoni Subject: Re: [PATCHv2 net-next 11/16] net: mvpp2: handle misc PPv2.1/PPv2.2 differences Message-ID: <20170107201057.GQ14217@n2100.armlinux.org.uk> References: <1482943592-12556-1-git-send-email-thomas.petazzoni@free-electrons.com> <1482943592-12556-12-git-send-email-thomas.petazzoni@free-electrons.com> <20170107093834.GJ14217@n2100.armlinux.org.uk> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20170107093834.GJ14217@n2100.armlinux.org.uk> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170107_121147_462330_85067B15 X-CRM114-Status: GOOD ( 20.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Yehuda Yitschak , Jason Cooper , Pawel Moll , Ian Campbell , netdev@vger.kernel.org, Hanna Hawa , Nadav Haklai , Rob Herring , Andrew Lunn , Kumar Gala , Gregory Clement , Stefan Chulski , Marcin Wojtas , "David S. Miller" , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP On Sat, Jan 07, 2017 at 09:38:34AM +0000, Russell King - ARM Linux wrote: > On Wed, Dec 28, 2016 at 05:46:27PM +0100, Thomas Petazzoni wrote: > > @@ -6511,7 +6515,9 @@ static int mvpp2_port_probe(struct platform_device *pdev, > > dev_err(&pdev->dev, "failed to init port %d\n", id); > > goto err_free_stats; > > } > > - mvpp2_port_power_up(port); > > + > > + if (priv->hw_version == MVPP21) > > + mvpp21_port_power_up(port); > > This has the side effect that nothing clears the port reset bit in the > GMAC, which means there's no hope of the interface working - with the > reset bit set, the port is well and truely held in "link down" state. > > In any case, the GMAC part is much the same as mvneta, and I think > that code should be shared rather than writing new versions of it. > There are some subtle differences between neta, pp2.1 and pp2.2, but > it's entirely doable (I have an implementation here as I wasn't going > to duplicate this code for my phylink conversion.) In addition to comphy configuration and the above, I also need the following to have working SGMII. The change of MACMODE is needed because uboot has configured the port for 10Gbase-R mode (it has a 10G PHY on it, but the PHY switches to SGMII in <10G modes.) The GMAC control register 4 is needed to properly configure for SGMII mode. I also included RGMII mode as well in there, as I expect you'd need it to have GMAC properly configured for RGMII. With this in place (and the other bits mentioned above), I can ping the clearfog switch on the other end of eth0's cable: # ping6 -I eth0 fe80::250:43ff:fe02:302 PING fe80::250:43ff:fe02:302(fe80::250:43ff:fe02:302) from fe80::200:ff:fe00:1 eth0: 56 data bytes 64 bytes from fe80::250:43ff:fe02:302: icmp_seq=1 ttl=64 time=0.297 ms diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index bc97eebf7eee..4b6ec6213e9c 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -345,7 +345,17 @@ #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \ MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK) +#define MVPP22_GMAC_CTRL_4_REG 0x90 +#define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0) +#define MVPP22_CTRL4_DP_CLK_SEL BIT(5) +#define MVPP22_CTRL4_SYNC_BYPASS BIT(6) +#define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7) + +#define MVPP22_XLG_CTRL3_REG 0x11c +#define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13) +#define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13) +/* offsets from iface_base */ #define MVPP22_SMI_MISC_CFG_REG 0x2a204 #define MVPP22_SMI_POLLING_EN BIT(10) @@ -4171,6 +4181,23 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port) { u32 val; + if (port->priv->hw_version == MVPP22) { + val = readl(port->base + MVPP22_XLG_CTRL3_REG); + val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; + val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; + writel(val, port->base + MVPP22_XLG_CTRL3_REG); + + val = readl(port->base + MVPP22_GMAC_CTRL_4_REG); + if (port->phy_interface == PHY_INTERFACE_MODE_RGMII) + val |= MVPP22_CTRL4_EXT_PIN_GMII_SEL; + else + val &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; + val &= ~MVPP22_CTRL4_DP_CLK_SEL; + val |= MVPP22_CTRL4_SYNC_BYPASS; + val |= MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; + writel(val, port->base + MVPP22_GMAC_CTRL_4_REG); + } + val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); switch (port->phy_interface) {