From patchwork Tue Jan 10 16:18:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Belloni X-Patchwork-Id: 9508129 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B460860231 for ; Tue, 10 Jan 2017 16:18:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A2EA0285A9 for ; Tue, 10 Jan 2017 16:18:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 95471285AC; Tue, 10 Jan 2017 16:18:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 144D7285A9 for ; Tue, 10 Jan 2017 16:18:51 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cQz8L-00019S-QY; Tue, 10 Jan 2017 16:18:49 +0000 Received: from mail.free-electrons.com ([62.4.15.54]) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cQz8H-0000tJ-2B for linux-arm-kernel@lists.infradead.org; Tue, 10 Jan 2017 16:18:47 +0000 Received: by mail.free-electrons.com (Postfix, from userid 110) id 447E020782; Tue, 10 Jan 2017 17:18:26 +0100 (CET) Received: from localhost (unknown [88.191.26.124]) by mail.free-electrons.com (Postfix) with ESMTPSA id 1A2C620712; Tue, 10 Jan 2017 17:18:26 +0100 (CET) Date: Tue, 10 Jan 2017 17:18:21 +0100 From: Alexandre Belloni To: Wenyou Yang Subject: Re: [PATCH 1/3] ARM: at91: flush the L2 cache before entering cpu idle Message-ID: <20170110161821.vp673jyfqx6s76pg@piout.net> References: <20170106065947.30631-1-wenyou.yang@atmel.com> <20170106065947.30631-2-wenyou.yang@atmel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20170106065947.30631-2-wenyou.yang@atmel.com> User-Agent: NeoMutt/20161126 (1.7.1) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170110_081845_401906_2AC7963D X-CRM114-Status: GOOD ( 20.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Russell King , Wenyou Yang , Nicolas Ferre , linux-kernel@vger.kernel.org, Rob Herring , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP I though a bit more about it, and I don't really like the new compatible string. I don't feel this should be necessary. What about the following: * to @@ -353,6 +362,11 @@ static __init void at91_dt_ramc(void) return; } + np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); + if (np) + at91_pm_data.has_l2_cache = true; + of_node_put(np); + at91_pm_set_standby(standby); } This has the following benefits: - everybody will have the fix, regardless of whether the dtb is updated - has_l2_cache can be used later in at91_pm_suspend instead of calling it unconditionnaly (I'll send a patch) On 06/01/2017 at 14:59:45 +0800, Wenyou Yang wrote : > For the SoCs such as SAMA5D2 and SAMA5D4 which have L2 cache, > flush the L2 cache first before entering the cpu idle. > > Signed-off-by: Wenyou Yang > --- > > arch/arm/mach-at91/pm.c | 19 +++++++++++++++++++ > drivers/memory/atmel-sdramc.c | 1 + > 2 files changed, 20 insertions(+) > > diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c > index b4332b727e9c..1a60dede1a01 100644 > --- a/arch/arm/mach-at91/pm.c > +++ b/arch/arm/mach-at91/pm.c > @@ -289,6 +289,24 @@ static void at91_ddr_standby(void) > at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); > } > > +static void at91_ddr_cache_standby(void) > +{ > + u32 saved_lpr; > + > + flush_cache_all(); > + outer_disable(); > + > + saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR); > + at91_ramc_write(0, AT91_DDRSDRC_LPR, (saved_lpr & > + (~AT91_DDRSDRC_LPCB)) | AT91_DDRSDRC_LPCB_SELF_REFRESH); > + > + cpu_do_idle(); > + > + at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr); > + > + outer_resume(); > +} > + > /* We manage both DDRAM/SDRAM controllers, we need more than one value to > * remember. > */ > @@ -324,6 +342,7 @@ static const struct of_device_id const ramc_ids[] __initconst = { > { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby }, > { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby }, > { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby }, > + { .compatible = "atmel,sama5d4-ddramc", .data = at91_ddr_cache_standby }, > { /*sentinel*/ } > }; > > diff --git a/drivers/memory/atmel-sdramc.c b/drivers/memory/atmel-sdramc.c > index b418b39af180..7e5c5c6c1348 100644 > --- a/drivers/memory/atmel-sdramc.c > +++ b/drivers/memory/atmel-sdramc.c > @@ -48,6 +48,7 @@ static const struct of_device_id atmel_ramc_of_match[] = { > { .compatible = "atmel,at91sam9260-sdramc", .data = &at91rm9200_caps, }, > { .compatible = "atmel,at91sam9g45-ddramc", .data = &at91sam9g45_caps, }, > { .compatible = "atmel,sama5d3-ddramc", .data = &sama5d3_caps, }, > + { .compatible = "atmel,sama5d4-ddramc", .data = &sama5d3_caps, }, > {}, > }; > > -- > 2.11.0 > diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index b4332b727e9c..0333aca63e44 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -53,6 +53,7 @@ extern void at91_pinctrl_gpio_resume(void); static struct { unsigned long uhp_udp_mask; int memctrl; + bool has_l2_cache; } at91_pm_data; void __iomem *at91_ramc_base[2]; @@ -267,6 +268,11 @@ static void at91_ddr_standby(void) u32 lpr0, lpr1 = 0; u32 saved_lpr0, saved_lpr1 = 0; + if (at91_pm_data.has_l2_cache) { + flush_cache_all(); + outer_disable(); + } + if (at91_ramc_base[1]) { saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; @@ -287,6 +293,9 @@ static void at91_ddr_standby(void) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); if (at91_ramc_base[1]) at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); + + if (at91_pm_data.has_l2_cache) + outer_resume(); } /* We manage both DDRAM/SDRAM controllers, we need more than one value