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[73.19.0.61]) by smtp.gmail.com with ESMTPSA id g70sm2927290pfb.50.2017.01.10.08.30.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 10 Jan 2017 08:30:37 -0800 (PST) From: Andrey Smirnov To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2] ARM: dts: imx6: Specify 'anatop-enable-bit' where appropriate Date: Tue, 10 Jan 2017 08:30:13 -0800 Message-Id: <20170110163015.22444-1-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.9.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170110_083059_025316_49BD8139 X-CRM114-Status: GOOD ( 11.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Andrey Smirnov , Russell King , linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Fabio Estevam , Shawn Guo , yurovsky@gmail.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP ENABLE_LINREG bit is implemented by 3P0, 1P1 and 2P5 regulators on i.MX6. This property is present in similar code in Fresscale BSP and made its way upstream in imx6ul.dtsi, so this patch adds this property to the rest of i.MX6 family for completness. Cc: yurovsky@gmail.com Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Rob Herring Cc: Mark Rutland Cc: Russell King Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov --- arch/arm/boot/dts/imx6qdl.dtsi | 3 +++ arch/arm/boot/dts/imx6sl.dtsi | 3 +++ arch/arm/boot/dts/imx6sx.dtsi | 3 +++ 3 files changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 89b834f..9702e18 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -635,6 +635,7 @@ anatop-min-bit-val = <4>; anatop-min-voltage = <800000>; anatop-max-voltage = <1375000>; + anatop-enable-bit = <0>; }; regulator-3p0 { @@ -649,6 +650,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2625000>; anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; }; regulator-2p5 { @@ -663,6 +665,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2000000>; anatop-max-voltage = <2750000>; + anatop-enable-bit = <0>; }; reg_arm: regulator-vddcore { diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 19cbd87..a478a06f 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -522,6 +522,7 @@ anatop-min-bit-val = <4>; anatop-min-voltage = <800000>; anatop-max-voltage = <1375000>; + anatop-enable-bit = <0>; }; regulator-3p0 { @@ -536,6 +537,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2625000>; anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; }; regulator-2p5 { @@ -550,6 +552,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2100000>; anatop-max-voltage = <2850000>; + anatop-enable-bit = <0>; }; reg_arm: regulator-vddcore { diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 10f3330..3de3cca 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -578,6 +578,7 @@ anatop-min-bit-val = <4>; anatop-min-voltage = <800000>; anatop-max-voltage = <1375000>; + anatop-enable-bit = <0>; }; regulator-3p0 { @@ -592,6 +593,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2625000>; anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; }; regulator-2p5 { @@ -606,6 +608,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2100000>; anatop-max-voltage = <2875000>; + anatop-enable-bit = <0>; }; reg_arm: regulator-vddcore {