From patchwork Wed Jan 11 14:41:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher Covington X-Patchwork-Id: 9510195 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1B91C6075C for ; Wed, 11 Jan 2017 14:42:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0DF1A28119 for ; Wed, 11 Jan 2017 14:42:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0155728613; Wed, 11 Jan 2017 14:42:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7AF2F28119 for ; Wed, 11 Jan 2017 14:42:31 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cRK6g-0003ZH-Lz; Wed, 11 Jan 2017 14:42:30 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cRK6B-0002bh-7n for linux-arm-kernel@lists.infradead.org; Wed, 11 Jan 2017 14:42:02 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 735E360430; Wed, 11 Jan 2017 14:41:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1484145702; bh=VFA6tAR9aspBvn7Cg25Ddxwa3b4GnElwa7iNeD9awlc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fXLNndi/QhDc0v/xVEfDXNx0wfreAr2CrG/Hxv9e9zXptxyuizWf5TcUdeYDfd1st qCB1xDUohJoUhQyrSZ5t5kAqVnIq9U6m3bOzHNjVPAHZWG9ulqJpI63GTHLsLg4Kp/ Jgu9FeYNhXpZ9mJ6wy8TM7JBXht34vMSniJVj+1E= Received: from illium.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: cov@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 0489161514; Wed, 11 Jan 2017 14:41:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1484145701; bh=VFA6tAR9aspBvn7Cg25Ddxwa3b4GnElwa7iNeD9awlc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MFklfmncVk+isuuBRGsIRU8w846KHJZxh1/dUHIvSd5fQ+Hi9uFPpgYu4bCUOc4SV eNZoCAuf1w2eJTjsDv5VqLmobrNyb2zIVtlZj3EcuEZ9Wn4xcS8xwILDU3WxX8pob2 xKzDgCnPkehj0FrXsW8eBM9AbrVyMwKi4BjP9Deo= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 0489161514 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=cov@codeaurora.org From: Christopher Covington To: Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , Christoffer Dall , Marc Zyngier , Catalin Marinas , Will Deacon , kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, shankerd@codeaurora.org, timur@codeaurora.org Subject: [PATCH v3 4/5] arm64: Use __tlbi_dsb() macros in KVM code Date: Wed, 11 Jan 2017 09:41:17 -0500 Message-Id: <20170111144118.17062-4-cov@codeaurora.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170111144118.17062-1-cov@codeaurora.org> References: <20170111144118.17062-1-cov@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170111_064159_440318_0E51F160 X-CRM114-Status: GOOD ( 11.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jon Masters , Mark Langsdorf , Christopher Covington , Mark Salter MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Refactor the KVM code to use the newly introduced __tlbi_dsb macros, which will allow an errata workaround that repeats tlbi dsb sequences to only change one location. This is not intended to change the generated assembly and comparing before and after vmlinux objdump shows no functional changes. Signed-off-by: Christopher Covington --- arch/arm64/kvm/hyp/tlb.c | 29 +++++++++++------------------ 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c index 88e2f2b..9669e4b 100644 --- a/arch/arm64/kvm/hyp/tlb.c +++ b/arch/arm64/kvm/hyp/tlb.c @@ -16,6 +16,7 @@ */ #include +#include void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) { @@ -30,19 +31,15 @@ void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) * We could do so much better if we had the VA as well. * Instead, we invalidate Stage-2 for this IPA, and the * whole of Stage-1. Weep... + * + * We have to ensure completion of the invalidation at Stage-2 with a + * DSB, since a table walk on another CPU could refill a TLB with a + * complete (S1 + S2) walk based on the old Stage-2 mapping if the + * Stage-1 invalidation happened first. */ ipa >>= 12; - asm volatile("tlbi ipas2e1is, %0" : : "r" (ipa)); - - /* - * We have to ensure completion of the invalidation at Stage-2, - * since a table walk on another CPU could refill a TLB with a - * complete (S1 + S2) walk based on the old Stage-2 mapping if - * the Stage-1 invalidation happened first. - */ - dsb(ish); - asm volatile("tlbi vmalle1is" : : ); - dsb(ish); + __tlbi_dsb(ipas2e1is, ish, ipa); + __tlbi_dsb(vmalle1is, ish); isb(); write_sysreg(0, vttbr_el2); @@ -57,8 +54,7 @@ void __hyp_text __kvm_tlb_flush_vmid(struct kvm *kvm) write_sysreg(kvm->arch.vttbr, vttbr_el2); isb(); - asm volatile("tlbi vmalls12e1is" : : ); - dsb(ish); + __tlbi_dsb(vmalls12e1is, ish); isb(); write_sysreg(0, vttbr_el2); @@ -72,8 +68,7 @@ void __hyp_text __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu) write_sysreg(kvm->arch.vttbr, vttbr_el2); isb(); - asm volatile("tlbi vmalle1" : : ); - dsb(nsh); + __tlbi_dsb(vmalle1, nsh); isb(); write_sysreg(0, vttbr_el2); @@ -82,7 +77,5 @@ void __hyp_text __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu) void __hyp_text __kvm_flush_vm_context(void) { dsb(ishst); - asm volatile("tlbi alle1is \n" - "ic ialluis ": : ); - dsb(ish); + __tlbi_asm_dsb("ic ialluis", alle1is, ish); }