From patchwork Sun Jan 15 11:47:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: afzal mohammed X-Patchwork-Id: 9517363 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7D7FD601DA for ; Sun, 15 Jan 2017 11:48:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 606C82840B for ; Sun, 15 Jan 2017 11:48:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5451228420; Sun, 15 Jan 2017 11:48:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D7DEC2840B for ; Sun, 15 Jan 2017 11:48:29 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cSjIQ-0004Mw-TB; Sun, 15 Jan 2017 11:48:26 +0000 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cSjIL-0004Lg-Vc for linux-arm-kernel@lists.infradead.org; Sun, 15 Jan 2017 11:48:23 +0000 Received: by mail-pg0-x241.google.com with SMTP id 75so2871991pgf.3 for ; Sun, 15 Jan 2017 03:47:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=U7kCi5gZAyrBk5/AgPikgRbK6eqq2KOnkRsuxyrOMrc=; b=SZRcyyws9SgjEcWZgGOPd5BWIvvm/xxindRSDBhcTIm/qtLYwVMvys1PvQDtVg4B27 pYRk5fVzoqDos6+ICH5WabpgE7nY43bWAR2dKmn30hbeBgc2G5THbxwK8mDn9JyBUzOs pvN5UvMYSYwCQPMv0BOwNKBenHXJhrZrn+x+EHHqHuSwhHubnlLPTJdDI1JOFbcv8rLi TSUd80qQeFLDshh/oSjSfwhv9YGuzoErzxZG4haOzXBiq65Hhe5s3fWa1qHxxjGoAoAA ZMZK5hDA0Jaww0tWPCCQ8Bcj818iue88zfyxDKgpgBmUDQE2KOxhBdw8+HE6U+KfmlKb 549A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=U7kCi5gZAyrBk5/AgPikgRbK6eqq2KOnkRsuxyrOMrc=; b=UrRUG51VYgjq9UMyAB0MAvEIcOO3QYo13SDubObnyNU6px8fqZW54iYakSqU3K8h4P EOkne6YaBAfqN8F1nw9nLCrRldLBExb4k3vmJuNb38VPCR7KmoE/ZG9hmpCA2IR3VgBB WSrWrzanTDT0CPKV5dYRMRxy2WXiF8S3wfFhS/YfH/WSWnvgkghDawGZRcXF+PyyxOpa 7YPjHJxVg31kedqpREtO7kZAVg9DoJ8OVeVOAo7eCxMtMbPn80lTrfz8e4Qm0UpNl9GK RzHmm169Y56tZ5ImEsmArZmYI9LQJ0vjtXSNc1mEOaYO8g5VRbKEYX2ymKy4aRi1EAU0 75xw== X-Gm-Message-State: AIkVDXIHD0grcXaFpoGlVtuU7UYevkitbXlLqzC1Rb4TyCZkjr9LnoOh9VV/1FKH70EqSA== X-Received: by 10.98.29.195 with SMTP id d186mr26571887pfd.144.1484480878003; Sun, 15 Jan 2017 03:47:58 -0800 (PST) Received: from localhost ([49.203.213.230]) by smtp.gmail.com with ESMTPSA id s136sm40476839pgs.46.2017.01.15.03.47.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 15 Jan 2017 03:47:57 -0800 (PST) Date: Sun, 15 Jan 2017 17:17:50 +0530 From: Afzal Mohammed To: Russell King - ARM Linux , Vladimir Murzin Subject: Re: [PATCH RFC 2/2] ARM: nommu: remap exception base address to RAM Message-ID: <20170115114750.GA5456@afzalpc> References: <20161211131028.3019-1-afzal.mohd.ma@gmail.com> <20161211131255.3221-1-afzal.mohd.ma@gmail.com> <20161213100226.GW14217@n2100.armlinux.org.uk> <20170107171339.GA5044@afzalpc> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20170107171339.GA5044@afzalpc> User-Agent: Mutt/1.5.24 (2015-08-30) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170115_034822_048748_CCED5012 X-CRM114-Status: GOOD ( 21.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, Arnd Bergmann , linux-kernel@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Hi, On Sat, Jan 07, 2017 at 10:43:39PM +0530, Afzal Mohammed wrote: > On Tue, Dec 13, 2016 at 10:02:26AM +0000, Russell King - ARM Linux wrote: > > Also, if the region setup for the vectors was moved as well, it would > > then be possible to check the ID registers to determine whether this > > is supported, and make the decision where to locate the vectors base > > more dynamically. > > This would affect Cortex-R's, which is a bit concerning due to lack of > those platforms with me, let me try to get it right. QEMU too doesn't seem to provide a Cortex-R target > Seems translating __setup_mpu() altogether to C afaics, a kind of C translation is already present as mpu_setup_region() in arch/arm/mm/nommu.c that takes care of MPU_RAM_REGION only. And that seems to be a kind of redundant as it is also done in asm at __setup_mpu(). Git blames asm & C to consecutive commits, that makes me a little shaky about the conclusion on it being redundant. > & installing at a later, but suitable place might be better. But looks like enabling MPU can't be moved to C & that would necessitate keeping at least some portion of__setu_mpu() in asm. Instead, moving region setup only for vectors to C as Russell suggested at first would have to be done. A kind of diff at the end is in my mind, with additional changes to handle the similar during secondary cpu bringup too. Thinking of invoking mpu_setup() from secondary_start_kernel() in arch/arm/kernel/smp.c, with mpu_setup() being slightly modified to avoid storing region details again when invoked by secondary cpu's. Vladimir, once changes are done after a revisit, i would need your help to test on Cortex-R. As an aside, wasn't aware of the fact that Cortex-R supports SMP Linux, had thought that, of !MMU one's, only Blackfin & J2 had it. > Also !MMU Kernel could boot on 3 ARM v7-A platforms - AM335x Beagle > Bone (A8), AM437x IDK (A9) & Vybrid VF610 (on A5 core, note that it > has M4 core too) Talking about Cortex-M, AMx3's too have it, to be specific M3, but they are not Linux-able unlike the one in VF610. Regards afzal --->8--- diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S index e0565d73e49e..f8ac79b6136d 100644 --- a/arch/arm/kernel/head-nommu.S +++ b/arch/arm/kernel/head-nommu.S @@ -249,20 +249,6 @@ ENTRY(__setup_mpu) setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled 2: isb - /* Vectors region */ - set_region_nr r0, #MPU_VECTORS_REGION - isb - /* Shared, inaccessible to PL0, rw PL1 */ - mov r0, #CONFIG_VECTORS_BASE @ Cover from VECTORS_BASE - ldr r5,=(MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL) - /* Writing N to bits 5:1 (RSR_SZ) --> region size 2^N+1 */ - mov r6, #(((2 * PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN) - - setup_region r0, r5, r6, MPU_DATA_SIDE @ VECTORS_BASE, PL0 NA, enabled - beq 3f @ Memory-map not unified - setup_region r0, r5, r6, MPU_INSTR_SIDE @ VECTORS_BASE, PL0 NA, enabled -3: isb - /* Enable the MPU */ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR bic r0, r0, #CR_BR @ Disable the 'default mem-map' diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index e82056df0635..7fe8906322d5 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -269,12 +269,19 @@ void __init mpu_setup(void) ilog2(memblock.memory.regions[0].size), MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL); if (region_err) { - panic("MPU region initialization failure! %d", region_err); + panic("MPU RAM region initialization failure! %d", region_err); } else { - pr_info("Using ARMv7 PMSA Compliant MPU. " - "Region independence: %s, Max regions: %d\n", - mpu_iside_independent() ? "Yes" : "No", - mpu_max_regions()); + region_err = mpu_setup_region(MPU_VECTORS_REGION, vectors_base, + ilog2(memblock.memory.regions[0].size), + MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL); + if (region_err) { + panic("MPU VECTOR region initialization failure! %d", + region_err); + } else { + pr_info("Using ARMv7 PMSA Compliant MPU. " + "Region independence: %s, Max regions: %d\n", + mpu_iside_independent() ? "Yes" : "No", + mpu_max_regions()); } } #else