From patchwork Sun Jan 29 13:24:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Keeping X-Patchwork-Id: 9544025 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 733CC60415 for ; Sun, 29 Jan 2017 13:28:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6583C204C1 for ; Sun, 29 Jan 2017 13:28:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5A39F27F88; Sun, 29 Jan 2017 13:28:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, T_DKIM_INVALID autolearn=no version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1A6C5204C1 for ; Sun, 29 Jan 2017 13:28:25 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cXpWo-0005gB-RU; Sun, 29 Jan 2017 13:28:22 +0000 Received: from dougal.metanate.com ([90.155.101.14] helo=metanate.com) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cXpUD-0003s7-4z; Sun, 29 Jan 2017 13:25:45 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=simple/simple; d=metanate.com; s=stronger; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=3yVdBFj+Xh8JOT2Aze1nCtIKNXz8+f0iOvix0zE56EI=; b=NlPbTzsuM54H9u1PIDpqw3fNBVMynozzq2AJzd/4D3kylH96iQsuZfe/kkok+wZrFovRmAwZh5n0uPZokKC+UiRZVMvAARUNmzhpOApnvLOs7pTGpAEHDR83CHvZC+VzBRh/PvajO26GzDAG6nPOZn0Di7euL4pRoisJ8/nTom9vFPoooZ1srhjuN6RrYoLRLHqreCKpiitZ+lH3rrjkPxbkJTlprhLg1cMpZB+Pkk0ILT+i/Y8cZh5VVs4s8sk4bF68amwtqqf27mWATzR7ROHU1o0qiDcom2bDrLIYbTVubCRy/3HQfJBinw+i9z089bVF+f61L8xGyld84hdHFg==; Received: from johnkeeping.plus.com ([81.174.171.191] helo=localhost.localdomain) by shrek.metanate.com with esmtpsa (TLSv1.2:DHE-RSA-AES128-GCM-SHA256:128) (Exim 4.83_RC2) (envelope-from ) id 1cXpTk-000362-QD; Sun, 29 Jan 2017 13:25:12 +0000 From: John Keeping To: Mark Yao Subject: [PATCH v3 16/24] drm/rockchip: dw-mipi-dsi: properly configure PHY timing Date: Sun, 29 Jan 2017 13:24:36 +0000 Message-Id: <20170129132444.25251-17-john@metanate.com> X-Mailer: git-send-email 2.11.0.197.gb556de5.dirty In-Reply-To: <20170129132444.25251-1-john@metanate.com> References: <20170129132444.25251-1-john@metanate.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170129_052541_484470_BBF1420E X-CRM114-Status: UNSURE ( 8.83 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, John Keeping , Chris Zhong , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP These values are specified as constant time periods but the PHY configuration is in terms of the current lane byte clock so using constant values guarantees that the timings will be outside the specification with some display configurations. Derive the necessary configuration from the byte clock in order to ensure that the PHY configuration is correct. Signed-off-by: John Keeping --- v3: - Wrap some long lines Unchanged in v2 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 39 ++++++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index cfe7e4ba305c..85edf6dd2bac 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -383,6 +383,26 @@ static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code, dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); } +/** + * ns2bc - Nanoseconds to byte clock cycles + */ +static inline unsigned int ns2bc(struct dw_mipi_dsi *dsi, int ns) +{ + unsigned long byte_clk_khz = dsi->lane_mbps * MSEC_PER_SEC / 8; + + return (ns * (byte_clk_khz / 1000) + 999) / 1000; +} + +/** + * ns2ui - Nanoseconds to UI time periods + */ +static inline unsigned int ns2ui(struct dw_mipi_dsi *dsi, int ns) +{ + unsigned long byte_clk_khz = dsi->lane_mbps * MSEC_PER_SEC; + + return (ns * (byte_clk_khz / 1000) + 999) / 1000; +} + static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) { int ret, testdin, vco, val; @@ -434,10 +454,21 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) SETRD_MAX | POWER_MANAGE | TER_RESISTORS_ON); - - dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf); - dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55); - dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa); + dw_mipi_dsi_phy_write(dsi, 0x60, TLP_PROGRAM_EN | ns2bc(dsi, 500)); + dw_mipi_dsi_phy_write(dsi, 0x61, THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); + dw_mipi_dsi_phy_write(dsi, 0x62, THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); + dw_mipi_dsi_phy_write(dsi, 0x63, THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); + dw_mipi_dsi_phy_write(dsi, 0x64, BIT(5) | ns2bc(dsi, 100)); + dw_mipi_dsi_phy_write(dsi, 0x65, BIT(5) | (ns2bc(dsi, 60) + 7)); + + dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | ns2bc(dsi, 500)); + dw_mipi_dsi_phy_write(dsi, 0x71, + THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 5)); + dw_mipi_dsi_phy_write(dsi, 0x72, + THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); + dw_mipi_dsi_phy_write(dsi, 0x73, + THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); + dw_mipi_dsi_phy_write(dsi, 0x74, BIT(5) | ns2bc(dsi, 100)); dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | PHY_UNRSTZ | PHY_UNSHUTDOWNZ);