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[6/8] arm64: dts: allwinner: add device node for R_PWM

Message ID 20170208100009.29362-6-icenowy@aosc.xyz (mailing list archive)
State New, archived
Headers show

Commit Message

Icenowy Zheng Feb. 8, 2017, 10 a.m. UTC 
Allwinner A64 SoC has two PWM controller, both are similar to the
controller in H3 SoC.

Add one of the controllers which lies in the "CPUs" part of the SoC.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Maxime Ripard Feb. 8, 2017, 10:17 a.m. UTC | #1 
On Wed, Feb 08, 2017 at 06:00:07PM +0800, Icenowy Zheng wrote:
> Allwinner A64 SoC has two PWM controller, both are similar to the
> controller in H3 SoC.
> 
> Add one of the controllers which lies in the "CPUs" part of the SoC.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 4b0baa79554c..6204aee5c6f4 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -432,5 +432,13 @@
>  			#size-cells = <0>;
>  			#gpio-cells = <3>;
>  		};
> +
> +		r_pwm: pwm@01f03800 {
> +			compatible = "allwinner,sun8i-h3-pwm";

Please add an a64 compatible there too.

> +			reg = <0x01f03800 0x8>;

The size is 0x400

Thanks,
Maxime
diff mbox

Patch

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 4b0baa79554c..6204aee5c6f4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -432,5 +432,13 @@ 
 			#size-cells = <0>;
 			#gpio-cells = <3>;
 		};
+
+		r_pwm: pwm@01f03800 {
+			compatible = "allwinner,sun8i-h3-pwm";
+			reg = <0x01f03800 0x8>;
+			clocks = <&osc24M>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
 	};
 };