| Message ID | 20170214235347.8812-1-cov@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Christopher Covington wrote: > The Qualcomm Datacenter Technologies QDF2400 family of SoCs contains a > custom (non-PrimeCell) implementation of the SBSA UART. Occasionally the > BUSY bit in the Flag Register gets stuck as 1, erratum 44 for both 2432v1 > and 2400v1 SoCs. Checking that the Transmit FIFO Empty (TXFE) bit is 0, > instead of checking that the BUSY bit is 1, works around the issue. To > facilitate this substitution when UART AMBA Port (UAP) data is available, > introduce vendor-specific inversion of Feature Register bits. For the > earlycon case, implement alternative putc and early_write functions. > Similar to what how ARMv8 ACPI PCI quirks are detected during MCFG parsing, > check the OEM fields of the Serial Port Console Redirection (SPCR) ACPI > table to determine if the current platform is known to be affected by the > erratum. Please break this up into paragraphs. > + if (!memcmp(table->header.oem_id, "QCOM ", ACPI_OEM_ID_SIZE)) > + if (!memcmp(table->header.oem_table_id, "QDF2432 ", > + ACPI_OEM_TABLE_ID_SIZE) || > + (!memcmp(table->header.oem_table_id, > + "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) && > + table->header.oem_revision == 0)) > + uart = "qdf2400_e44"; > + Hey, you just wrote this And it looks crazy But here's my function So call it, maybe? static bool needs_qdf2400_e44(struct acpi_table_header *h) { const char *id; /* The erratum only applies to Qualcomm Technologies SOCs */ if (memcmp(h->oem_id, "QCOM ", ACPI_OEM_ID_SIZE)) return False; id = h->oem_table_id; if (!memcmp(id, "QDF2432 ", ACPI_OEM_TABLE_ID_SIZE)) return True; if (!memcmp(id, "QDF2000 ", ACPI_OEM_TABLE_ID_SIZE) && h->oem_revision == 0) return True; return False; } ... if (needs_qdf2400_e44(&table->header)) uart = "qdf2400_e44"; > +/* > + * Erratum 44 for QDF2432v1 and QDF2400v1 SoCs describes the BUSY bit as > + * occasionally getting stuck as 1. To avoid the potential for a hang, check > + * TXFE == 0 instead of BUSY == 1. This may not be suitable for all UART > + * implementations, so only do so if an affected platform is detected in > + * parse_spcr(). > + */ > +static bool qdf2400_e44 = false; Please rename this to needs_qdf2400_e44 > static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { > [REG_DR] = UART01x_DR, > [REG_ST_DMAWM] = ST_UART011_DMAWM, > @@ -1518,7 +1543,8 @@ static unsigned int pl011_tx_empty(struct uart_port *port) > { > struct uart_amba_port *uap = > container_of(port, struct uart_amba_port, port); > - unsigned int status = pl011_read(uap, REG_FR); > + /* Allow feature register bits to be inverted to work around errata */ Blank line above the comment, please. > + unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; > return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? > 0 : TIOCSER_TEMT; > } > @@ -2215,10 +2241,12 @@ pl011_console_write(struct console *co, const char *s, unsigned int count) > uart_console_write(&uap->port, s, count, pl011_console_putchar); > > /* > - * Finally, wait for transmitter to become empty > - * and restore the TCR > + * Finally, wait for transmitter to become empty and restore the > + * TCR. Allow feature register bits to be inverted to work around > + * errata. > */ > - while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) > + while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) > + & uap->vendor->fr_busy) > cpu_relax(); > if (!uap->vendor->always_enabled) > pl011_write(old_cr, uap, REG_CR); > @@ -2340,8 +2368,13 @@ static int __init pl011_console_match(struct console *co, char *name, int idx, > resource_size_t addr; > int i; > > - if (strcmp(name, "pl011") != 0) > + if (strcmp(name, "qdf2400_e44") == 0) { > + if (!qdf2400_e44) > + pr_info("UART: Working around QDF2400 SoC erratum 44"); Just use pr_once(), and you can skip the "if (!qdf2400_e44)". Although I don't understand why you need to do that. pl011_console_match() should only be called once anyway, right? > + qdf2400_e44 = true; > + } else if (strcmp(name, "pl011") != 0) { > return -ENODEV; > + } > > if (uart_parse_earlycon(options, &iotype, &addr, &options)) > return -ENODEV; > @@ -2383,6 +2416,25 @@ static struct console amba_console = { > > #define AMBA_CONSOLE (&amba_console) > > +static void qdf2400_e44_putc(struct uart_port *port, int c) > +{ > + while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) > + cpu_relax(); > + if (port->iotype == UPIO_MEM32) > + writel(c, port->membase + UART01x_DR); > + else > + writeb(c, port->membase + UART01x_DR); I think you can ignore the UPIO_MEM32 test and always use writel(), even on the QDF2400.
Hi, On Tue, Feb 14, 2017 at 08:39:40PM -0600, Timur Tabi wrote: > Christopher Covington wrote: > >+ if (!memcmp(table->header.oem_id, "QCOM ", ACPI_OEM_ID_SIZE)) > >+ if (!memcmp(table->header.oem_table_id, "QDF2432 ", > >+ ACPI_OEM_TABLE_ID_SIZE) || > >+ (!memcmp(table->header.oem_table_id, > >+ "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) && > >+ table->header.oem_revision == 0)) > >+ uart = "qdf2400_e44"; > >+ Thanks for reworking this. I'm much happier with this than the MIDR check. Splitting out the test into its own function, as Timur suggested, would generally be nicer. Minor comments on that below. > static bool needs_qdf2400_e44(struct acpi_table_header *h) > { This is detecting the presence of the erratum so, has_qdf2400_e44() or needs__qdf2400_e44_workaround() would be better names. I'd personally prefer the former, but either is fine. > const char *id; > > /* The erratum only applies to Qualcomm Technologies SOCs */ > if (memcmp(h->oem_id, "QCOM ", ACPI_OEM_ID_SIZE)) > return False; > > id = h->oem_table_id; > > if (!memcmp(id, "QDF2432 ", ACPI_OEM_TABLE_ID_SIZE)) > return True; > > if (!memcmp(id, "QDF2000 ", ACPI_OEM_TABLE_ID_SIZE) && > h->oem_revision == 0) > return True; > > return False; > } s/False/false/g s/True/true/g With that, this looks fine to me. I'm not too familiar with the pl011 driver. On the assumption the other changes have already been vetted: Acked-by: Mark Rutland <mark.rutland@arm.com> Thanks, Mark.
On 2017-02-14 21:39, Timur Tabi wrote: > Christopher Covington wrote: >> The Qualcomm Datacenter Technologies QDF2400 family of SoCs contains a >> custom (non-PrimeCell) implementation of the SBSA UART. Occasionally >> the >> BUSY bit in the Flag Register gets stuck as 1, erratum 44 for both >> 2432v1 >> and 2400v1 SoCs. Checking that the Transmit FIFO Empty (TXFE) bit is >> 0, >> instead of checking that the BUSY bit is 1, works around the issue. To >> facilitate this substitution when UART AMBA Port (UAP) data is >> available, >> introduce vendor-specific inversion of Feature Register bits. For the >> earlycon case, implement alternative putc and early_write functions. >> Similar to what how ARMv8 ACPI PCI quirks are detected during MCFG >> parsing, >> check the OEM fields of the Serial Port Console Redirection (SPCR) >> ACPI >> table to determine if the current platform is known to be affected by >> the >> erratum. > > Please break this up into paragraphs. Sure >> + if (!memcmp(table->header.oem_id, "QCOM ", ACPI_OEM_ID_SIZE)) >> + if (!memcmp(table->header.oem_table_id, "QDF2432 ", >> + ACPI_OEM_TABLE_ID_SIZE) || >> + (!memcmp(table->header.oem_table_id, >> + "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) && >> + table->header.oem_revision == 0)) >> + uart = "qdf2400_e44"; >> + > > Hey, you just wrote this > And it looks crazy > But here's my function > So call it, maybe? > > static bool needs_qdf2400_e44(struct acpi_table_header *h) > { > const char *id; > > /* The erratum only applies to Qualcomm Technologies SOCs */ > if (memcmp(h->oem_id, "QCOM ", ACPI_OEM_ID_SIZE)) > return False; > > id = h->oem_table_id; > > if (!memcmp(id, "QDF2432 ", ACPI_OEM_TABLE_ID_SIZE)) > return True; > > if (!memcmp(id, "QDF2000 ", ACPI_OEM_TABLE_ID_SIZE) && > h->oem_revision == 0) > return True; > > return False; > } > > ... > > if (needs_qdf2400_e44(&table->header)) > uart = "qdf2400_e44"; Sure >> +/* >> + * Erratum 44 for QDF2432v1 and QDF2400v1 SoCs describes the BUSY bit >> as >> + * occasionally getting stuck as 1. To avoid the potential for a >> hang, check >> + * TXFE == 0 instead of BUSY == 1. This may not be suitable for all >> UART >> + * implementations, so only do so if an affected platform is detected >> in >> + * parse_spcr(). >> + */ >> +static bool qdf2400_e44 = false; > > Please rename this to needs_qdf2400_e44 Nothing needs QDF2400 erratum 44. Software should try to detect the presence of the erratum. So I think qdf2400_e44_detected or qdf2400_e44_present would make sense. But those suffixes don't add substantial value in my opinion. Affected hardware needs the *workaround* to the erratum. So I think needs_qdf2400_e44_workaround makes sense. But it's pretty lengthy. If qdf2400_e44 is too cryptic, how about qdf2400_erratum_44? >> static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { >> [REG_DR] = UART01x_DR, >> [REG_ST_DMAWM] = ST_UART011_DMAWM, >> @@ -1518,7 +1543,8 @@ static unsigned int pl011_tx_empty(struct >> uart_port *port) >> { >> struct uart_amba_port *uap = >> container_of(port, struct uart_amba_port, port); >> - unsigned int status = pl011_read(uap, REG_FR); >> + /* Allow feature register bits to be inverted to work around errata >> */ > > Blank line above the comment, please. Sure >> + unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; >> return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? >> 0 : TIOCSER_TEMT; >> } >> @@ -2215,10 +2241,12 @@ pl011_console_write(struct console *co, const >> char *s, unsigned int count) >> uart_console_write(&uap->port, s, count, pl011_console_putchar); >> >> /* >> - * Finally, wait for transmitter to become empty >> - * and restore the TCR >> + * Finally, wait for transmitter to become empty and restore the >> + * TCR. Allow feature register bits to be inverted to work around >> + * errata. >> */ >> - while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) >> + while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) >> + & uap->vendor->fr_busy) >> cpu_relax(); >> if (!uap->vendor->always_enabled) >> pl011_write(old_cr, uap, REG_CR); >> @@ -2340,8 +2368,13 @@ static int __init pl011_console_match(struct >> console *co, char *name, int idx, >> resource_size_t addr; >> int i; >> >> - if (strcmp(name, "pl011") != 0) >> + if (strcmp(name, "qdf2400_e44") == 0) { >> + if (!qdf2400_e44) >> + pr_info("UART: Working around QDF2400 SoC erratum 44"); > > Just use pr_once(), and you can skip the "if (!qdf2400_e44)". > Although I don't understand why you need to do that. > pl011_console_match() should only be called once anyway, right? Sure. In my debugging I saw it printed 3 times. Keep in mind there are at least two UARTs, one for the DB9 socket on the front of the chassis and connected to the BMC for Serial Over LAN. Maybe the first hit was from earlycon or SPCR parsing, I don't really know. >> + qdf2400_e44 = true; >> + } else if (strcmp(name, "pl011") != 0) { >> return -ENODEV; >> + } >> >> if (uart_parse_earlycon(options, &iotype, &addr, &options)) >> return -ENODEV; >> @@ -2383,6 +2416,25 @@ static struct console amba_console = { >> >> #define AMBA_CONSOLE (&amba_console) >> >> +static void qdf2400_e44_putc(struct uart_port *port, int c) >> +{ >> + while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) >> + cpu_relax(); >> + if (port->iotype == UPIO_MEM32) >> + writel(c, port->membase + UART01x_DR); >> + else >> + writeb(c, port->membase + UART01x_DR); > > I think you can ignore the UPIO_MEM32 test and always use writel(), > even on the QDF2400. Sure Cheers, Cov -- Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
Christopher Covington wrote: > Nothing needs QDF2400 erratum 44. Software should try to detect the presence > of the erratum. So I think qdf2400_e44_detected or qdf2400_e44_present would > make sense. But those suffixes don't add substantial value in my opinion. I'd be okay with qdf2400_e44_detected or qdf2400_e44_present. I think it's a lot clearer. Another idea is "has_qdf2400_e44".
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index a71b8095dbd8..bc3d086bc624 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -68,3 +68,5 @@ stable kernels. | | | | | | Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | | Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | +| Qualcomm Tech. | QDF2432v1 UART | SoC E44 | N/A | +| Qualcomm Tech. | QDF2400v1 UART | SoC E44 | N/A | diff --git a/drivers/acpi/spcr.c b/drivers/acpi/spcr.c index b8019c4c1d38..59064f10353f 100644 --- a/drivers/acpi/spcr.c +++ b/drivers/acpi/spcr.c @@ -93,6 +93,14 @@ int __init parse_spcr(bool earlycon) goto done; } + if (!memcmp(table->header.oem_id, "QCOM ", ACPI_OEM_ID_SIZE)) + if (!memcmp(table->header.oem_table_id, "QDF2432 ", + ACPI_OEM_TABLE_ID_SIZE) || + (!memcmp(table->header.oem_table_id, + "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) && + table->header.oem_revision == 0)) + uart = "qdf2400_e44"; + snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype, table->serial_port.address, baud_rate); diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index d4171d71a258..4208012d52b2 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -97,6 +97,7 @@ struct vendor_data { unsigned int fr_dsr; unsigned int fr_cts; unsigned int fr_ri; + unsigned int inv_fr; bool access_32b; bool oversampling; bool dma_threshold; @@ -141,6 +142,30 @@ static struct vendor_data vendor_sbsa = { .fixed_options = true, }; +/* + * Erratum 44 for QDF2432v1 and QDF2400v1 SoCs describes the BUSY bit as + * occasionally getting stuck as 1. To avoid the potential for a hang, check + * TXFE == 0 instead of BUSY == 1. This may not be suitable for all UART + * implementations, so only do so if an affected platform is detected in + * parse_spcr(). + */ +static bool qdf2400_e44 = false; + +static struct vendor_data vendor_qdt_qdf2400_e44 = { + .reg_offset = pl011_std_offsets, + .fr_busy = UART011_FR_TXFE, + .fr_dsr = UART01x_FR_DSR, + .fr_cts = UART01x_FR_CTS, + .fr_ri = UART011_FR_RI, + .inv_fr = UART011_FR_TXFE, + .access_32b = true, + .oversampling = false, + .dma_threshold = false, + .cts_event_workaround = false, + .always_enabled = true, + .fixed_options = true, +}; + static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { [REG_DR] = UART01x_DR, [REG_ST_DMAWM] = ST_UART011_DMAWM, @@ -1518,7 +1543,8 @@ static unsigned int pl011_tx_empty(struct uart_port *port) { struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port); - unsigned int status = pl011_read(uap, REG_FR); + /* Allow feature register bits to be inverted to work around errata */ + unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; } @@ -2215,10 +2241,12 @@ pl011_console_write(struct console *co, const char *s, unsigned int count) uart_console_write(&uap->port, s, count, pl011_console_putchar); /* - * Finally, wait for transmitter to become empty - * and restore the TCR + * Finally, wait for transmitter to become empty and restore the + * TCR. Allow feature register bits to be inverted to work around + * errata. */ - while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) + while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) + & uap->vendor->fr_busy) cpu_relax(); if (!uap->vendor->always_enabled) pl011_write(old_cr, uap, REG_CR); @@ -2340,8 +2368,13 @@ static int __init pl011_console_match(struct console *co, char *name, int idx, resource_size_t addr; int i; - if (strcmp(name, "pl011") != 0) + if (strcmp(name, "qdf2400_e44") == 0) { + if (!qdf2400_e44) + pr_info("UART: Working around QDF2400 SoC erratum 44"); + qdf2400_e44 = true; + } else if (strcmp(name, "pl011") != 0) { return -ENODEV; + } if (uart_parse_earlycon(options, &iotype, &addr, &options)) return -ENODEV; @@ -2383,6 +2416,25 @@ static struct console amba_console = { #define AMBA_CONSOLE (&amba_console) +static void qdf2400_e44_putc(struct uart_port *port, int c) +{ + while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) + cpu_relax(); + if (port->iotype == UPIO_MEM32) + writel(c, port->membase + UART01x_DR); + else + writeb(c, port->membase + UART01x_DR); + while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE)) + cpu_relax(); +} + +static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n) +{ + struct earlycon_device *dev = con->data; + + uart_console_write(&dev->port, s, n, qdf2400_e44_putc); +} + static void pl011_putc(struct uart_port *port, int c) { while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) @@ -2408,7 +2460,8 @@ static int __init pl011_early_console_setup(struct earlycon_device *device, if (!device->port.membase) return -ENODEV; - device->con->write = pl011_early_write; + device->con->write = qdf2400_e44 ? + qdf2400_e44_early_write : pl011_early_write; return 0; } OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); @@ -2645,7 +2698,7 @@ static int sbsa_uart_probe(struct platform_device *pdev) uap->port.irq = ret; uap->reg_offset = vendor_sbsa.reg_offset; - uap->vendor = &vendor_sbsa; + uap->vendor = qdf2400_e44 ? &vendor_qdt_qdf2400_e44 : &vendor_sbsa; uap->fifosize = 32; uap->port.iotype = vendor_sbsa.access_32b ? UPIO_MEM32 : UPIO_MEM; uap->port.ops = &sbsa_uart_pops;