From patchwork Fri Feb 17 17:37:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 9580443 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A4FE06043A for ; Fri, 17 Feb 2017 17:40:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9745028755 for ; Fri, 17 Feb 2017 17:40:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8AF7128762; Fri, 17 Feb 2017 17:40:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 94C4228755 for ; Fri, 17 Feb 2017 17:40:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=TlYHbclE03ApRRle+Xeb7mUhvQdQNQTHHeCt29AVaVw=; b=b2CBMLAr9rBpxMBzR7wpVnNAZ4 RdEy76EFmEHS+wsKJRG9ZxaXjQqIYyFjWUocxxT5eoEHFfE1qJX1GgtygF6NzPRnDo+GpMY+XKYFy zNSca30Z3coJIxP35yXqR0gVVCp+WkqnZm7KS5J+ZqhFpZaJPkNRz/OMWkd9JEv2W9DhPsiVZ4FcT WKiVMB5gq7jnJujp44ww8eoXFg9YgIj3WRbmS3pFOqR3QUcblSxOAS0eaQPW1Tru9kQUIS6uejDJn 9IfgS01ux9at/NLl0UAhokW8j4PPSGOiTKKtj0quxvNbuwS9DIPKPHQSx5OjWUpB8wdIOY4p6lfO5 h/5G9hVA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cemWF-0006FC-HM; Fri, 17 Feb 2017 17:40:31 +0000 Received: from forward19h.cmail.yandex.net ([2a02:6b8:0:f35::a4]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cemW0-0004xR-PY for linux-arm-kernel@lists.infradead.org; Fri, 17 Feb 2017 17:40:28 +0000 Received: from smtp1h.mail.yandex.net (smtp1h.mail.yandex.net [IPv6:2a02:6b8:0:f05::115]) by forward19h.cmail.yandex.net (Yandex) with ESMTP id D68A121812; Fri, 17 Feb 2017 20:39:53 +0300 (MSK) Received: from smtp1h.mail.yandex.net (localhost.localdomain [127.0.0.1]) by smtp1h.mail.yandex.net (Yandex) with ESMTP id 89B368C0D4C; Fri, 17 Feb 2017 20:39:45 +0300 (MSK) Received: by smtp1h.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id FT0kHVt6CM-de1CBBPY; Fri, 17 Feb 2017 20:39:44 +0300 (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aosc.xyz; s=mail; t=1487353185; bh=D9xhNd45k0s9OJDdqL+w90HHevqPwXKnB1uwe8TCAlc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=j0vSL9dUX1bLqNyxU6S9/kz5NgzPsrdaHPbpmftyO6dSmlU6hbBwlug25/C/8cylZ MrCgWNmb+OdwyhYcPFMysNBBC4B3JpiG3QmGMyW03QRXp/ePey2ftGJ+u1ZSlMknyM DxYbPqvdCaj34RiOEcgs+OBTZqzijz+4q8J7NYas= Authentication-Results: smtp1h.mail.yandex.net; dkim=pass header.i=@aosc.xyz X-Yandex-ForeignMX: FR X-Yandex-Suid-Status: 1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 1130000036118848 From: Icenowy Zheng To: Maxime Ripard , Chen-Yu Tsai , Kishon Vijay Abraham I , Linus Walleij Subject: [PATCH 3/9] pinctrl: sunxi: add support for R40 pinctrl Date: Sat, 18 Feb 2017 01:37:16 +0800 Message-Id: <20170217173722.6477-4-icenowy@aosc.xyz> X-Mailer: git-send-email 2.11.1 In-Reply-To: <20170217173722.6477-1-icenowy@aosc.xyz> References: <20170217173722.6477-1-icenowy@aosc.xyz> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170217_094017_350090_CCF8BBA3 X-CRM114-Status: GOOD ( 12.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Allwinner R40 have a pin controller similar to A20, only added 8-bit eMMC function to mmc2 at PC bank. Add support for it in the already renamed sunxi-a20-r40 driver via variant framework. Signed-off-by: Icenowy Zheng --- drivers/pinctrl/sunxi/pinctrl-sunxi-a20-r40.c | 161 ++++++++++++++++++++------ drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 + 2 files changed, 125 insertions(+), 38 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi-a20-r40.c b/drivers/pinctrl/sunxi/pinctrl-sunxi-a20-r40.c index b6f4c68ffb39..a925e6b835bc 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi-a20-r40.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi-a20-r40.c @@ -18,7 +18,7 @@ #include "pinctrl-sunxi.h" -static const struct sunxi_desc_pin sun7i_a20_pins[] = { +static const struct sunxi_desc_pin sunxi_a20_r40_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -146,7 +146,10 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ + SUNXI_FUNCTION_VARIANT(0x3, + "pll-lock-dbg", + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -154,11 +157,21 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */ + SUNXI_FUNCTION_VARIANT(0x2, + "pwm", /* PWM0 */ + PINCTRL_SUN7I_A20), + SUNXI_FUNCTION_VARIANT(0x3, + "pwm", /* PWM0 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0"), /* TX */ + SUNXI_FUNCTION_VARIANT(0x2, + "ir0", /* TX */ + PINCTRL_SUN7I_A20), + SUNXI_FUNCTION_VARIANT(0x3, + "pwm", /* PWM1 */ + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "spdif")), /* MCLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -187,11 +200,17 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0")), /* DO1 */ + SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */ + SUNXI_FUNCTION_VARIANT(0x4, + "pwm", /* PWM6 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0")), /* DO2 */ + SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */ + SUNXI_FUNCTION_VARIANT(0x4, + "pwm", /* PWM7 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -201,12 +220,16 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s0"), /* DI */ SUNXI_FUNCTION(0x3, "ac97"), /* DI */ - SUNXI_FUNCTION(0x4, "spdif")), /* DI */ + SUNXI_FUNCTION_VARIANT(0x4, + "spdif", /* DI */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ - SUNXI_FUNCTION(0x4, "spdif")), /* DO */ + SUNXI_FUNCTION_VARIANT(0x4, + "spdif", /* DO */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -247,7 +270,9 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart0"), /* TX */ - SUNXI_FUNCTION(0x3, "ir1")), /* TX */ + SUNXI_FUNCTION_VARIANT(0x2, + "ir1", /* TX */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -280,7 +305,10 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */ + SUNXI_FUNCTION(0x2, "nand0"), /* NRE# */ + SUNXI_FUNCTION_VARIANT(0x3, + "mmc2", /* DS */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -314,19 +342,31 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ + SUNXI_FUNCTION_VARIANT(0x3, + "mmc2", /* D4 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ + SUNXI_FUNCTION_VARIANT(0x3, + "mmc2", /* D5 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ + SUNXI_FUNCTION_VARIANT(0x3, + "mmc2", /* D6 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ + SUNXI_FUNCTION_VARIANT(0x3, + "mmc2", /* D7 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -366,7 +406,10 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */ + SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */ + SUNXI_FUNCTION_VARIANT(0x3, + "mmc2", /* RST */ + PINCTRL_SUN8I_R40)), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -667,14 +710,20 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_FUNCTION(0x2, "ts1"), /* D5 */ SUNXI_FUNCTION(0x3, "csi1"), /* D5 */ SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ - SUNXI_FUNCTION(0x5, "csi0")), /* D13 */ + SUNXI_FUNCTION(0x5, "csi0"), /* D13 */ + SUNXI_FUNCTION_VARIANT(0x6, + "bist", /* RESULT0 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "ts1"), /* D6 */ SUNXI_FUNCTION(0x3, "csi1"), /* D6 */ SUNXI_FUNCTION(0x4, "uart4"), /* TX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D14 */ + SUNXI_FUNCTION(0x5, "csi0"), /* D14 */ + SUNXI_FUNCTION_VARIANT(0x6, + "bist", /* RESULT1 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -730,7 +779,9 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */ SUNXI_FUNCTION(0x4, "uart5"), /* TX */ - SUNXI_FUNCTION(0x5, "ms"), /* BS */ + SUNXI_FUNCTION_VARIANT(0x5, + "ms", /* BS */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */ SUNXI_FUNCTION(0x7, "csi1")), /* D6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), @@ -738,7 +789,9 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */ SUNXI_FUNCTION(0x4, "uart5"), /* RX */ - SUNXI_FUNCTION(0x5, "ms"), /* CLK */ + SUNXI_FUNCTION_VARIANT(0x5, + "ms", /* CLK */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */ SUNXI_FUNCTION(0x7, "csi1")), /* D7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), @@ -747,7 +800,9 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */ SUNXI_FUNCTION(0x3, "emac"), /* ERXD3 */ SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */ - SUNXI_FUNCTION(0x5, "ms"), /* D0 */ + SUNXI_FUNCTION_VARIANT(0x5, + "ms", /* D0 */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */ SUNXI_FUNCTION(0x7, "csi1")), /* D8 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), @@ -756,7 +811,9 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */ SUNXI_FUNCTION(0x3, "emac"), /* ERXD2 */ SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */ - SUNXI_FUNCTION(0x5, "ms"), /* D1 */ + SUNXI_FUNCTION_VARIANT(0x5, + "ms", /* D1 */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */ SUNXI_FUNCTION(0x7, "csi1")), /* D9 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), @@ -765,7 +822,9 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */ SUNXI_FUNCTION(0x3, "emac"), /* ERXD1 */ SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */ - SUNXI_FUNCTION(0x5, "ms"), /* D2 */ + SUNXI_FUNCTION_VARIANT(0x5, + "ms", /* D2 */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */ SUNXI_FUNCTION(0x7, "csi1")), /* D10 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), @@ -774,7 +833,9 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */ SUNXI_FUNCTION(0x3, "emac"), /* ERXD0 */ SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */ - SUNXI_FUNCTION(0x5, "ms"), /* D3 */ + SUNXI_FUNCTION_VARIANT(0x5, + "ms", /* D3 */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */ SUNXI_FUNCTION(0x7, "csi1")), /* D11 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12), @@ -816,6 +877,9 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */ SUNXI_FUNCTION(0x3, "emac"), /* ETXD2 */ SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */ + SUNXI_FUNCTION_VARIANT(0x5, + "sim", /* DET */ + PINCTRL_SUN8I_R40), SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */ SUNXI_FUNCTION(0x7, "csi1")), /* D16 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17), @@ -1020,37 +1084,58 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */ SUNXI_FUNCTION(0x3, "uart7"), /* TX */ - SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */ + SUNXI_FUNCTION_VARIANT(0x4, + "hdmi", /* HSCL */ + PINCTRL_SUN7I_A20), + SUNXI_FUNCTION_VARIANT(0x6, + "pwm", /* PWM2 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */ SUNXI_FUNCTION(0x3, "uart7"), /* RX */ - SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */ + SUNXI_FUNCTION_VARIANT(0x4, + "hdmi", /* HSDA */ + PINCTRL_SUN7I_A20), + SUNXI_FUNCTION_VARIANT(0x6, + "pwm", /* PWM3 */ + PINCTRL_SUN8I_R40)), }; -static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = { - .pins = sun7i_a20_pins, - .npins = ARRAY_SIZE(sun7i_a20_pins), +static const struct sunxi_pinctrl_desc sunxi_a20_r40_pinctrl_data = { + .pins = sunxi_a20_r40_pins, + .npins = ARRAY_SIZE(sunxi_a20_r40_pins), .irq_banks = 1, }; -static int sun7i_a20_pinctrl_probe(struct platform_device *pdev) +static int sunxi_a20_r40_pinctrl_probe(struct platform_device *pdev) { - return sunxi_pinctrl_init(pdev, - &sun7i_a20_pinctrl_data); + unsigned long variant = + (unsigned long)of_device_get_match_data(&pdev->dev); + + return sunxi_pinctrl_init_with_variant(pdev, + &sunxi_a20_r40_pinctrl_data, + variant); } -static const struct of_device_id sun7i_a20_pinctrl_match[] = { - { .compatible = "allwinner,sun7i-a20-pinctrl", }, +static const struct of_device_id sunxi_a20_r40_pinctrl_match[] = { + { + .compatible = "allwinner,sun7i-a20-pinctrl", + .data = (void *) PINCTRL_SUN7I_A20, + }, + { + .compatible = "allwinner,sun8i-r40-pinctrl", + .data = (void *) PINCTRL_SUN8I_R40, + }, {} }; -static struct platform_driver sun7i_a20_pinctrl_driver = { - .probe = sun7i_a20_pinctrl_probe, +static struct platform_driver sunxi_a20_r40_pinctrl_driver = { + .probe = sunxi_a20_r40_pinctrl_probe, .driver = { - .name = "sun7i-a20-pinctrl", - .of_match_table = sun7i_a20_pinctrl_match, + .name = "sunxi-a20-r40-pinctrl", + .of_match_table = sunxi_a20_r40_pinctrl_match, }, }; -builtin_platform_driver(sun7i_a20_pinctrl_driver); +builtin_platform_driver(sunxi_a20_r40_pinctrl_driver); diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 56be35387ccf..4d1afa29d744 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -85,6 +85,8 @@ #define PINCTRL_SUN5I_A10S BIT(1) #define PINCTRL_SUN5I_A13 BIT(2) #define PINCTRL_SUN5I_GR8 BIT(3) +#define PINCTRL_SUN7I_A20 BIT(4) +#define PINCTRL_SUN8I_R40 BIT(5) struct sunxi_desc_function { unsigned long variant;