From patchwork Wed Feb 22 02:29:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 9586085 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7BEDC6020B for ; Wed, 22 Feb 2017 02:34:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 606072865A for ; Wed, 22 Feb 2017 02:34:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5509528782; Wed, 22 Feb 2017 02:34:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C84A82865A for ; Wed, 22 Feb 2017 02:34:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=t8TpjyDk0Vk9sn7kL8DZKCjZ6c9VHN9nDoQ9ml28oDg=; b=Jvx1QpsJT86w9y zWW0b9ahzNvWGIgzaG0FHVDpcd6Oo3hzYcy+QlRHROMO2MEZ9F9iHVfn3HlCahtkjR+TUu6d2vZJa h5w90hPJp55SssKQBicGJ14liAKqeZNhhQdrRcswzc0J1oFqYzTAqEMBo3oBxByh8JjCgBAaje7HX Z7xsaR+8lKcy0TIhTUe645y7jjfGkjAvNVJC5S9mcZzmaaQoZW14S+CSbHpqkvhT2z9fnTwiwcShg v4ZKwzNHIUZG1Fuv8tZuLMtFZqOgTMjdqjJZ9q6NBJ/sw69ZBAJkJcg3dJLrD5bbttUTORTLmhGPd xeAcSYIkk8OrfusceKXg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cgMkh-0000sz-SZ; Wed, 22 Feb 2017 02:33:59 +0000 Received: from mx2.suse.de ([195.135.220.15]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cgMhT-0007ID-2q for linux-arm-kernel@lists.infradead.org; Wed, 22 Feb 2017 02:30:45 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 25E63ADC7; Wed, 22 Feb 2017 02:29:58 +0000 (UTC) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 7/8] ARM64: dts: marvell: Add IAP140 and Andromeda Box Edge Date: Wed, 22 Feb 2017 03:29:27 +0100 Message-Id: <20170222022929.10540-8-afaerber@suse.de> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170222022929.10540-1-afaerber@suse.de> References: <20170222022929.10540-1-afaerber@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170221_183039_665284_71F2FCB9 X-CRM114-Status: GOOD ( 18.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , info@andromedabox.org, Eric Miao , devicetree@vger.kernel.org, Catalin Marinas , Will Deacon , linux-kernel@vger.kernel.org, Haojian Zhuang , Rob Herring , =?UTF-8?q?Andreas=20F=C3=A4rber?= Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP PPI interrupts 11, 10, 9 are guesses, and so are the second two memory regions of the GIC. Signed-off-by: Andreas Färber --- v1 -> v2: * Updated for ARCH_MMP, added Makefile comment * Adopted "marvell" vendor prefix (Thomas) * Disabled smmu in .dtsi, re-enabled in .dts * Enabled asram node * Added adma, timer, pinctrl nodes arch/arm64/boot/dts/marvell/Makefile | 3 + .../boot/dts/marvell/iap140-andromeda-box-edge.dts | 80 +++++++ arch/arm64/boot/dts/marvell/iap140.dtsi | 241 +++++++++++++++++++++ 3 files changed, 324 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/iap140-andromeda-box-edge.dts create mode 100644 arch/arm64/boot/dts/marvell/iap140.dtsi diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 3e6ce6c..fa1bf06 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -2,6 +2,9 @@ dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-dmp.dtb dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-stb.dtb +# MMP SoC Family +dtb-$(CONFIG_ARCH_MMP) += iap140-andromeda-box-edge.dtb + # Mvebu SoC Family dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb diff --git a/arch/arm64/boot/dts/marvell/iap140-andromeda-box-edge.dts b/arch/arm64/boot/dts/marvell/iap140-andromeda-box-edge.dts new file mode 100644 index 0000000..0b0b150 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/iap140-andromeda-box-edge.dts @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2016-2017 Andreas Färber + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +/memreserve/ 0x09000000 0x01000000; +/memreserve/ 0x0a000000 0x00080000; + +#include "iap140.dtsi" + +/ { + compatible = "marvell,andromeda-box-edge", "marvell,iap140"; + model = "Andromeda Box Edge"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; +}; + +&pmx { + pinctrl-single,gpio-range = <&range 55 55 0>, + <&range 110 32 0>, + <&range 52 1 0>; +}; + +&smmu { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/marvell/iap140.dtsi b/arch/arm64/boot/dts/marvell/iap140.dtsi new file mode 100644 index 0000000..a0cefa6 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/iap140.dtsi @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2016-2017 Andreas Färber + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +/ { + compatible = "marvell,iap140"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + smmu: iommu@c0010000 { + compatible = "arm,mmu-400"; + reg = <0x0 0xc0010000 0x0 0x10000>; + #global-interrupts = <1>; + interrupts = , + ; + status = "disabled"; + }; + + adma: dma-controller@d128d800 { + compatible = "marvell,adma-1.0"; + reg = <0x0 0xd128d800 0x0 0x100>; + interrupts = ; + asram = <&asram>; + }; + + asram: sram@d12a0000 { + compatible = "mmio-sram"; + reg = <0x0 0xd12a0000 0x0 0x10000>; + }; + + gic: interrupt-controller@d1df9000 { + compatible = "arm,gic-400"; + reg = <0x0 0xd1df9000 0x0 0x1000>, + <0x0 0xd1dfa000 0x0 0x2000>, + <0x0 0xd1dfc000 0x0 0x2000>, + <0x0 0xd1dfe000 0x0 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + apb@d4000000 { + compatible = "simple-bus"; + reg = <0x0 0xd4000000 0x0 0x00200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xd4000000 0x00200000>; + + pdma: dma-controller@0 { + compatible = "marvell,pdma-1.0"; + reg = <0x0 0x10000>; + interrupts = ; + #dma-cells = <2>; + #dma-channels = <30>; + }; + + timer0: timer@14000 { + compatible = "mrvl,mmp-timer"; + reg = <0x14000 0xc8>; + interrupts = , + ; + status = "disabled"; + }; + + timer1: timer@16000 { + compatible = "mrvl,mmp-timer"; + reg = <0x16000 0xc8>; + interrupts = , + ; + status = "disabled"; + }; + + uart0: serial@17000 { + compatible = "mrvl,mmp-uart"; + reg = <0x17000 0x1000>; + interrupts = ; + dmas = <&pdma 21 1>, + <&pdma 22 1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@18000 { + compatible = "mrvl,mmp-uart"; + reg = <0x18000 0x1000>; + interrupts = ; + dmas = <&pdma 23 1>, + <&pdma 24 1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + pmx: pinmux@1e000 { + compatible = "pinconf-single"; + reg = <0x1e000 0x330>; + #address-cells = <1>; + #size-cells = <1>; + #gpio-range-cells = <3>; + ranges; + + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + }; + + timer2: timer@1f000 { + compatible = "mrvl,mmp-timer"; + reg = <0x1f000 0xc8>; + status = "disabled"; + }; + + uart2: serial@36000 { + compatible = "mrvl,mmp-uart"; + reg = <0x36000 0x1000>; + interrupts = ; + dmas = <&pdma 4 1>, + <&pdma 5 1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + }; + + axi@d4200000 { + compatible = "simple-bus"; + reg = <0x0 0xd4200000 0x0 0x00200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xd4200000 0x00200000>; + }; + }; +};