From patchwork Mon Feb 27 19:27:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 9593819 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9C405604AB for ; Mon, 27 Feb 2017 19:28:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 88B0328488 for ; Mon, 27 Feb 2017 19:28:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7D3F5284C9; Mon, 27 Feb 2017 19:28:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0820928488 for ; Mon, 27 Feb 2017 19:28:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=cXgkgsKw3h7jIyymG5c16g4Z+x77/7Ng3+guce1Yn7E=; b=L99KdKTed+yTOs27kUR+4i00Xy 6bt+KxCwmQfMcDv0plGNO4ygFSO16fu2TiRX91pXoczjKJ7jzXNP1aso/1IuI0I3rgU2hRNcpx4Vj TOYEker0FCLGIJxRlN0ZDu9LZ6kg+OiDOoD1NYfTpSqohwbwAEnGpwK6CTjsJ2sRljjHTcCFmWbYc P29MRzgW6febpbi3/cAsWomD6QaWVoMMiSiRcFi3KMND4ZTdrQ3GuMO3FnWXaV1MX+xu11VI6urQq DG/qIMLgfj4Omq1+MgUXfXgYwglOhlkAXhqDOCehhxjXIU/+a8Fpqw1IDiATm7SOLWLNB3QH+RGqY A3dhJvLA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1ciQyV-0001og-8s; Mon, 27 Feb 2017 19:28:47 +0000 Received: from forward16j.cmail.yandex.net ([2a02:6b8:0:1630::f3]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1ciQyA-0001Yw-4M for linux-arm-kernel@lists.infradead.org; Mon, 27 Feb 2017 19:28:29 +0000 Received: from smtp1m.mail.yandex.net (smtp1m.mail.yandex.net [IPv6:2a02:6b8:0:2519::121]) by forward16j.cmail.yandex.net (Yandex) with ESMTP id 5929721F26; Mon, 27 Feb 2017 22:28:00 +0300 (MSK) Received: from smtp1m.mail.yandex.net (localhost.localdomain [127.0.0.1]) by smtp1m.mail.yandex.net (Yandex) with ESMTP id CD3D063C0D26; Mon, 27 Feb 2017 22:27:54 +0300 (MSK) Received: by smtp1m.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id 7Z3HtOy2lJ-Rm7SVlTk; Mon, 27 Feb 2017 22:27:53 +0300 (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aosc.xyz; s=mail; t=1488223674; bh=SjcrQ2kE9lrDWaK2Uzc719WgYM6jCR6YZQHSGL3FPow=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=XJTCg3ZR8p24ZmA+egOPZUed7QGFbGJmhKhT8BQC9Qe5vM0Y7FAAXKB1Zp3HBwwmX ClWdHmBMGQ7EtdyhQccTzT4bZeBg1VwxmGFW1JkTk4EIEgT7tHI5Zos9i9KK6UZFs5 rxJQXsAtP3gPH6ulVyRKJZIqlgpAqdSrec5noPfA= Authentication-Results: smtp1m.mail.yandex.net; dkim=pass header.i=@aosc.xyz X-Yandex-ForeignMX: US X-Yandex-Suid-Status: 1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 1130000036118848 From: Icenowy Zheng To: Srinivas Kandagatla , Maxime Ripard , Rob Herring , Chen-Yu Tsai Subject: [PATCH v5 2/3] nvmem: sunxi-sid: add support for H3's SID controller Date: Tue, 28 Feb 2017 03:27:14 +0800 Message-Id: <20170227192715.50198-2-icenowy@aosc.xyz> X-Mailer: git-send-email 2.11.1 In-Reply-To: <20170227192715.50198-1-icenowy@aosc.xyz> References: <20170227192715.50198-1-icenowy@aosc.xyz> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170227_112826_655261_3F681A2D X-CRM114-Status: GOOD ( 18.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The H3 SoC have a bigger SID controller, which has its direct read address at 0x200 position in the SID block, not 0x0. Also, H3 SID controller has some silicon bug that makes the direct read value wrong at cold boot, add code to workaround the bug. (This bug has already been fixed on A64 and later SoCs) Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard --- Changes in v5: - Removed some bits in binding documentation. - Removed some default values in cfg struct. Changes in v4: - Use readl_poll_timeout. - Do register offset in sunxi_sid_read. - Merge SUN8I_SID_OP_LOCK and SUN8I_SID_LOCK_SHIFT into one macro. - Drop the result of register-based read operation. .../bindings/nvmem/allwinner,sunxi-sid.txt | 6 ++- drivers/nvmem/sunxi_sid.c | 62 ++++++++++++++++++++++ 2 files changed, 67 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt index d543ed3f5363..ef06d061913c 100644 --- a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt +++ b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt @@ -1,7 +1,11 @@ Allwinner sunxi-sid Required properties: -- compatible: "allwinner,sun4i-a10-sid" or "allwinner,sun7i-a20-sid" +- compatible: Should be one of the following: + "allwinner,sun4i-a10-sid" + "allwinner,sun7i-a20-sid" + "allwinner,sun8i-h3-sid" + - reg: Should contain registers location and length = Data cells = diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c index 69524b67007f..0d6648be93b8 100644 --- a/drivers/nvmem/sunxi_sid.c +++ b/drivers/nvmem/sunxi_sid.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include @@ -25,6 +26,15 @@ #include #include +/* Registers and special values for doing register-based SID readout on H3 */ +#define SUN8I_SID_PRCTL 0x40 +#define SUN8I_SID_RDKEY 0x60 + +#define SUN8I_SID_OFFSET_MASK 0x1FF +#define SUN8I_SID_OFFSET_SHIFT 16 +#define SUN8I_SID_OP_LOCK (0xAC << 8) +#define SUN8I_SID_READ BIT(1) + static struct nvmem_config econfig = { .name = "sunxi-sid", .read_only = true, @@ -34,11 +44,14 @@ static struct nvmem_config econfig = { }; struct sunxi_sid_cfg { + u32 value_offset; u32 size; + bool need_register_readout; }; struct sunxi_sid { void __iomem *base; + u32 value_offset; }; /* We read the entire key, due to a 32 bit read alignment requirement. Since we @@ -63,12 +76,36 @@ static int sunxi_sid_read(void *context, unsigned int offset, struct sunxi_sid *sid = context; u8 *buf = val; + /* Offset the read operation to the real position of SID */ + offset += sid->value_offset; + while (bytes--) *buf++ = sunxi_sid_read_byte(sid, offset++); return 0; } +static int sun8i_sid_register_readout(const struct sunxi_sid *sid, + const unsigned int word) +{ + u32 reg_val; + int ret; + + /* Set word, lock access, and set read command */ + reg_val = (word & SUN8I_SID_OFFSET_MASK) + << SUN8I_SID_OFFSET_SHIFT; + reg_val |= SUN8I_SID_OP_LOCK | SUN8I_SID_READ; + writel(reg_val, sid->base + SUN8I_SID_PRCTL); + + ret = readl_poll_timeout(sid->base + SUN8I_SID_PRCTL, reg_val, + !(reg_val & SUN8I_SID_READ), 100, 250000); + if (ret) + return ret; + + writel(0, sid->base + SUN8I_SID_PRCTL); + return 0; +} + static int sunxi_sid_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -86,6 +123,7 @@ static int sunxi_sid_probe(struct platform_device *pdev) cfg = of_device_get_match_data(dev); if (!cfg) return -EINVAL; + sid->value_offset = cfg->value_offset; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); sid->base = devm_ioremap_resource(dev, res); @@ -94,6 +132,23 @@ static int sunxi_sid_probe(struct platform_device *pdev) size = cfg->size; + if (cfg->need_register_readout) { + /* + * H3's SID controller have a bug that the value at 0x200 + * offset is not the correct value when the hardware is reseted. + * However, after doing a register-based read operation, the + * value become right. + * Do a full read operation here, but ignore its value + * (as it's more fast to read by direct MMIO value than + * with registers) + */ + for (i = 0; i < (size >> 2); i++) { + ret = sun8i_sid_register_readout(sid, i); + if (ret) + return ret; + } + } + econfig.size = size; econfig.dev = dev; econfig.reg_read = sunxi_sid_read; @@ -138,9 +193,16 @@ static const struct sunxi_sid_cfg sun7i_a20_cfg = { .size = 0x200, }; +static const struct sunxi_sid_cfg sun8i_h3_cfg = { + .value_offset = 0x200, + .size = 0x100, + .need_register_readout = true, +}; + static const struct of_device_id sunxi_sid_of_match[] = { { .compatible = "allwinner,sun4i-a10-sid", .data = &sun4i_a10_cfg }, { .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg }, + { .compatible = "allwinner,sun8i-h3-sid", .data = &sun8i_h3_cfg }, {/* sentinel */}, }; MODULE_DEVICE_TABLE(of, sunxi_sid_of_match);