From patchwork Mon Feb 27 19:54:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 9593879 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 09C6B60471 for ; Mon, 27 Feb 2017 20:01:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EDFCD28491 for ; Mon, 27 Feb 2017 20:01:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E1B972849E; Mon, 27 Feb 2017 20:01:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8CF2228491 for ; Mon, 27 Feb 2017 20:01:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=uBv43q7VsxzoIbamP46NPQNOiOnD6OW5gE7i7MrJUCg=; b=t6MU0lJHc/ofQFqwue1PngYnng CswohvpL44WdCEJ3ff3Clk742Cvz8s463T3QvSILv0vZfOIN2Lxgak2G6U/Rt8FprfNohQNScReIf nMcCzzv/QIazGGTSpaEWt3tgEqtKf8wumviMdoUWwGpLO4FgnY0ZefasGdWm3jwE27FP/Z6gr3RFR 5gUeqUMgtV4P/76jHgwVx13DR5HK6y3r/rfWIHJMmJMjfZ0i8eCEyn9RES1rrvE12B4i43ZBnfSKd mG6iDqaSX8+hKoOlmmpjJZw+vYe1brk2IN6yztJsY+B5An7zLBxcuk4623YjA10XxkDEYmclak+Sw 1LWlBc2w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1ciRU2-0003JT-LV; Mon, 27 Feb 2017 20:01:22 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1ciRRJ-0007wm-4m for linux-arm-kernel@lists.infradead.org; Mon, 27 Feb 2017 19:58:35 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 35E8F1435; Mon, 27 Feb 2017 11:58:17 -0800 (PST) Received: from e106794-lin.cambridge.arm.com (e106794-lin.cambridge.arm.com [10.1.210.60]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8B9F93F3E1; Mon, 27 Feb 2017 11:58:14 -0800 (PST) From: Jean-Philippe Brucker To: Subject: [RFC PATCH 05/30] iommu/arm-smmu-v3: Disable tagged pointers when ATS is in use Date: Mon, 27 Feb 2017 19:54:16 +0000 Message-Id: <20170227195441.5170-6-jean-philippe.brucker@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170227195441.5170-1-jean-philippe.brucker@arm.com> References: <20170227195441.5170-1-jean-philippe.brucker@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170227_115833_321064_D60CAA0E X-CRM114-Status: GOOD ( 14.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lorenzo Pieralisi , Shanker Donthineni , kvm@vger.kernel.org, Catalin Marinas , Joerg Roedel , Sinan Kaya , Will Deacon , iommu@lists.linux-foundation.org, Harv Abdulhamid , Alex Williamson , linux-pci@vger.kernel.org, Bjorn Helgaas , Robin Murphy , David Woodhouse , linux-arm-kernel@lists.infradead.org, Nate Watterson MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The ARM architecture has a "Top Byte Ignore" (TBI) option that makes the MMU mask out bits [63:56] of an address, allowing a userspace application to store data in its pointers. The ATS doesn't have an architected mechanism to enable TBI, and might create ATC entries for addresses that include a tag. Software would then have to send ATC invalidation packets for each 255 possible alias of an address, or just wipe the whole address space. This is not a viable option, so disable TBI when ATS is in use. It is unclear for the moment how this restriction will affect user applications. One example I can imagine (with my complete lack of knowledge about JIT engines and their use of tagged pointers) is a JIT translating a WebCL applications that uses SVM. Since this kind of interpreted language doesn't expose addresses, the interpreter and SVM implementations will be given the opportunity to do the right thing and remove tags before handing pointers to devices. Ideally we should remove TBI only for domains that are susceptible to use ATS. But at the point we're writing the context descriptor of a domain, we are still probing the first device in the group. If that device doesn't have an ATC but the next one does, we would then have to clear the TBI bit, invalidate the ATCs of previous devices, and notify the drivers that their devices cannot use tagged pointers anymore. Such a level of complexity doesn't make any sense here since it is unlikely devices will use tagged pointers at all. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index e7b940146ae3..06b29d4fcf65 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -987,7 +987,7 @@ static void arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, } /* Context descriptor manipulation functions */ -static u64 arm_smmu_cpu_tcr_to_cd(u64 tcr) +static u64 arm_smmu_cpu_tcr_to_cd(struct arm_smmu_device *smmu, u64 tcr) { u64 val = 0; @@ -1000,7 +1000,8 @@ static u64 arm_smmu_cpu_tcr_to_cd(u64 tcr) val |= ARM_SMMU_TCR2CD(tcr, EPD0); val |= ARM_SMMU_TCR2CD(tcr, EPD1); val |= ARM_SMMU_TCR2CD(tcr, IPS); - val |= ARM_SMMU_TCR2CD(tcr, TBI0); + if (!(smmu->features & ARM_SMMU_FEAT_ATS)) + val |= ARM_SMMU_TCR2CD(tcr, TBI0); return val; } @@ -1014,7 +1015,7 @@ static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu, * We don't need to issue any invalidation here, as we'll invalidate * the STE when installing the new entry anyway. */ - val = arm_smmu_cpu_tcr_to_cd(cfg->cd.tcr) | + val = arm_smmu_cpu_tcr_to_cd(smmu, cfg->cd.tcr) | #ifdef __BIG_ENDIAN CTXDESC_CD_0_ENDI | #endif