From patchwork Mon Mar 6 17:17:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 9607213 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B6AE8601D2 for ; Mon, 6 Mar 2017 17:22:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D74A9205FB for ; Mon, 6 Mar 2017 17:22:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CC1CA23B23; Mon, 6 Mar 2017 17:22:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4BF77205FB for ; Mon, 6 Mar 2017 17:22:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=pqy4QZU8+AqX/lgkReeRCzok64yWaqITOpC3gHTYSUw=; b=qpNstNZ4OkCWGbcZikcGxCUbsm aMv0OF1nFFRksKcSNUMoCGUeJEDqUiOC2no16/CtuoMXaH7XB5gQ8UQboHPoJN9aO97N6c090cC7i BE2Qr4wtsSMzlpx21/3Y71JOOAcOoYHSRbo+um+Gh5MYbfpcs6paS+ee9m1XKJOkT1wGdT/M3rH64 OcosiWx0cNRJ39X4y9Wdg3ZbF3bsZwS09L3G0eepRovY9ieMbr25IzuDuGbBqKq69n7WpY1hir1sW UJF9r0Yl57f4krE0uCYcDArZkA95pvijTfkhFQK+ozohXRRZPcmzS2gRpIy1ibNJQL74PAfEwONcf YMiRE8YQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1ckwKx-0006DG-Dk; Mon, 06 Mar 2017 17:22:19 +0000 Received: from forward13h.cmail.yandex.net ([87.250.230.155]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1ckwJE-0004up-8c for linux-arm-kernel@lists.infradead.org; Mon, 06 Mar 2017 17:20:34 +0000 Received: from smtp3h.mail.yandex.net (smtp3h.mail.yandex.net [IPv6:2a02:6b8:0:f05::117]) by forward13h.cmail.yandex.net (Yandex) with ESMTP id ADA8821548; Mon, 6 Mar 2017 20:20:07 +0300 (MSK) Received: from smtp3h.mail.yandex.net (localhost.localdomain [127.0.0.1]) by smtp3h.mail.yandex.net (Yandex) with ESMTP id C570644091B; Mon, 6 Mar 2017 20:19:59 +0300 (MSK) Received: by smtp3h.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id dSnQ21pEEq-JqgSoldE; Mon, 06 Mar 2017 20:19:57 +0300 (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aosc.xyz; s=mail; t=1488820798; bh=YlVkXFb0DHJ2jHufSkt7larj7GslnkOF3MCzReM5MoQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=HwlthAvK6PGn/VjK20Sah45bvOi1AKyqk642vetTWDtlhFA54p6fZYfz9wipIzK9j HskQ7pNcabBR7h2YkQkdUj+p/9CCgx3AzxQWtTrux1Aw8xs9VkxPVfTFdjw1PsyNgu 0Lq6LC2AGK1VH6LuZikWo88w92KFHeE+yRpTX7Is= Authentication-Results: smtp3h.mail.yandex.net; dkim=pass header.i=@aosc.xyz X-Yandex-ForeignMX: US X-Yandex-Suid-Status: 1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 1130000036118848 From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai Subject: [PATCH v8 5/6] arm64: dts: allwinner: h5: add Allwinner H5 .dtsi Date: Tue, 7 Mar 2017 01:17:49 +0800 Message-Id: <20170306171750.7491-6-icenowy@aosc.xyz> X-Mailer: git-send-email 2.11.1 In-Reply-To: <20170306171750.7491-1-icenowy@aosc.xyz> References: <20170306171750.7491-1-icenowy@aosc.xyz> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170306_092032_750108_9B1E5213 X-CRM114-Status: GOOD ( 16.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Andre Przywara , linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Andre Przywara The Allwinner H5 SoC is pin-compatible to the H3 SoC, but uses Cortex-A53 cores instead. Based on the now shared base .dtsi describing the common peripherals describe the H5 specific nodes on top of that. That symlinks in the sunxi-h3-h5.dtsi from the arch/arm tree. Signed-off-by: Andre Przywara [Icenowy: add H5 pinctrl compatible, and changes for my h3-h5 dtsi refactor, commit message changed to meet new arm64 naming scheme, drop H3 pinctrl compatible because of interrupt bank change, drop H3 ccu compatible because of clock change, drop ccu node as it come into h3-h5 dtsi] Signed-off-by: Icenowy Zheng --- Changes in v8: - Add h5: in commit message. Changes in v6: - Dropped GIC node as it's in sunxi-h3-h5.dtsi now - Fixed some words in commit message, thanks to Rask Ingemann Lambertsen Changes in v3: - Dropped sun5i-a13-mmc, sun8i-h3-ccu compatibles. - Used sun50i-{h5,a64}-emmc compatible for mmc2. Changes in v2: - Dropped sun8i-h3-pinctrl compatible, as the interrupt of H3 and H5 is incompatible arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 124 +++++++++++++++++++++++++ arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi | 1 + 2 files changed, 125 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi create mode 120000 arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi new file mode 100644 index 000000000000..4d314a253fd9 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2016 ARM Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sunxi-h3-h5.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; + +&ccu { + compatible = "allwinner,sun50i-h5-ccu"; +}; + +&mmc0 { + compatible = "allwinner,sun50i-h5-mmc", + "allwinner,sun50i-a64-mmc"; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; +}; + +&mmc1 { + compatible = "allwinner,sun50i-h5-mmc", + "allwinner,sun50i-a64-mmc"; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; +}; + +&mmc2 { + compatible = "allwinner,sun50i-h5-emmc", + "allwinner,sun50i-a64-emmc"; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; +}; + +&pio { + compatible = "allwinner,sun50i-h5-pinctrl"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi new file mode 120000 index 000000000000..036f01dc2b9b --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi @@ -0,0 +1 @@ +../../../../arm/boot/dts/sunxi-h3-h5.dtsi \ No newline at end of file