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b=ctjh2LqmYnJPb4xXWu+GIHQF05XEAlYD2KrgLkGu9pT6hV5q18hpPdBEuXBXGaOc6 v81j8JAwPIUQXtia/2BYFxqJGtdJ/r9fwlegvJlMCG437pKxMcjMmzJ9lTnxUjjqEF XN92udKyGsu29OF2q2dWpN2NdBdJyOQUFXqauWt4= Authentication-Results: smtp2j.mail.yandex.net; dkim=pass header.i=@aosc.xyz X-Yandex-ForeignMX: US X-Yandex-Suid-Status: 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 1130000036118848 From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Kishon Vijay Abraham I , Hans de Goede Subject: [PATCH v4 3/8] phy: sun4i-usb: add PHYCTL offset for H3 SoC Date: Mon, 20 Mar 2017 00:19:46 +0800 Message-Id: <20170319161951.55834-4-icenowy@aosc.xyz> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170319161951.55834-1-icenowy@aosc.xyz> References: <20170319161951.55834-1-icenowy@aosc.xyz> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170319_162242_797299_6B9D3C68 X-CRM114-Status: UNSURE ( 9.69 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The config structure of H3 in phy-sun4i-usb driver have the PHYCTL register offset missing. Add it. Because it's a SoC after A33, its PHYCTL offset should be 0x10. Signed-off-by: Icenowy Zheng --- New patch in v4. drivers/phy/phy-sun4i-usb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c index 62b4d25448c6..a650f283f6ff 100644 --- a/drivers/phy/phy-sun4i-usb.c +++ b/drivers/phy/phy-sun4i-usb.c @@ -821,6 +821,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { .num_phys = 4, .type = sun8i_h3_phy, .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, .enable_pmu_unk1 = true, };