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[217.61.220.45]) by smtp.gmail.com with ESMTPSA id f48sm24358252wrf.17.2017.03.21.04.05.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 21 Mar 2017 04:05:36 -0700 (PDT) From: Christoffer Dall To: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/5] KVM: arm64: vgic: Rename vgic_v3_cpu to vgic_cpu Date: Tue, 21 Mar 2017 12:05:28 +0100 Message-Id: <20170321110530.15857-4-cdall@linaro.org> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170321110530.15857-1-cdall@linaro.org> References: <20170321110530.15857-1-cdall@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170321_040559_120906_9DDBD399 X-CRM114-Status: GOOD ( 12.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christoffer Dall , kvm@vger.kernel.org, Marc Zyngier , Andre Przywara , Vijaya.Kumar@cavium.com, Eric Auger MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP We have a temporary variable that points to the vgic_cpu structure, and not the GICv3 specific part, which is a bit misleading compared to the convention in the rest of the code. As we are about to mess with the logic of userspace access, let's rename this. No functional change. Signed-off-by: Christoffer Dall --- arch/arm64/kvm/vgic-sys-reg-v3.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kvm/vgic-sys-reg-v3.c b/arch/arm64/kvm/vgic-sys-reg-v3.c index 48848db..33f111c 100644 --- a/arch/arm64/kvm/vgic-sys-reg-v3.c +++ b/arch/arm64/kvm/vgic-sys-reg-v3.c @@ -20,7 +20,7 @@ static bool write_gic_ctlr(struct kvm_vcpu *vcpu, u32 val) { - struct vgic_cpu *vgic_v3_cpu = &vcpu->arch.vgic_cpu; + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; u32 host_pri_bits, host_id_bits, host_seis, host_a3v, seis, a3v; struct vgic_vmcr vmcr; @@ -32,17 +32,17 @@ static bool write_gic_ctlr(struct kvm_vcpu *vcpu, u32 val) */ host_pri_bits = ((val & ICC_CTLR_EL1_PRI_BITS_MASK) >> ICC_CTLR_EL1_PRI_BITS_SHIFT) + 1; - if (host_pri_bits > vgic_v3_cpu->num_pri_bits) + if (host_pri_bits > vgic_cpu->num_pri_bits) return false; - vgic_v3_cpu->num_pri_bits = host_pri_bits; + vgic_cpu->num_pri_bits = host_pri_bits; host_id_bits = (val & ICC_CTLR_EL1_ID_BITS_MASK) >> ICC_CTLR_EL1_ID_BITS_SHIFT; - if (host_id_bits > vgic_v3_cpu->num_id_bits) + if (host_id_bits > vgic_cpu->num_id_bits) return false; - vgic_v3_cpu->num_id_bits = host_id_bits; + vgic_cpu->num_id_bits = host_id_bits; host_seis = ((kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_SEIS_MASK) >> ICH_VTR_SEIS_SHIFT); @@ -70,15 +70,15 @@ static bool write_gic_ctlr(struct kvm_vcpu *vcpu, u32 val) static u32 read_gic_ctlr(struct kvm_vcpu *vcpu) { - struct vgic_cpu *vgic_v3_cpu = &vcpu->arch.vgic_cpu; + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; u32 val = 0; struct vgic_vmcr vmcr; vgic_get_vmcr(vcpu, &vmcr); - val |= (vgic_v3_cpu->num_pri_bits - 1) << + val |= (vgic_cpu->num_pri_bits - 1) << ICC_CTLR_EL1_PRI_BITS_SHIFT; - val |= vgic_v3_cpu->num_id_bits << ICC_CTLR_EL1_ID_BITS_SHIFT; + val |= vgic_cpu->num_id_bits << ICC_CTLR_EL1_ID_BITS_SHIFT; val |= ((kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_SEIS_MASK) >> ICH_VTR_SEIS_SHIFT) << ICC_CTLR_EL1_SEIS_SHIFT;