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b=HPgDegbPdvOTc0BJ6DhMUiTo6dw3ZBmlqiBupGrapv5blgyvA1OmdSDDABFSBKsP7 sAoCOlBVmjZSY5w8RE08vXPvjZ2pgppo9TKIy5+npYX1E+NE7m6XUDreLNLkQZClAv W2QrKnNHFxIIoJNd2NP3RXUJzPGSeeP+JqwvwpEA= Authentication-Results: smtp1p.mail.yandex.net; dkim=pass header.i=@aosc.xyz X-Yandex-ForeignMX: US X-Yandex-Suid-Status: 1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 1130000036118848 From: Icenowy Zheng To: Kishon Vijay Abraham I , Rob Herring , Maxime Ripard , Chen-Yu Tsai Subject: [PATCH v5 5/8] ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5 Date: Sat, 25 Mar 2017 22:50:12 +0800 Message-Id: <20170325145015.22076-6-icenowy@aosc.xyz> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170325145015.22076-1-icenowy@aosc.xyz> References: <20170325145015.22076-1-icenowy@aosc.xyz> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170325_105334_242322_A78CCEEC X-CRM114-Status: UNSURE ( 9.97 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Allwinner H3/H5 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI or MUSB controller. Add device nodes for these controllers. Signed-off-by: Icenowy Zheng --- Changes in v5: - Change the size of &usb_otg address space from 0x0400 to 0x400. Changes in v4: - Add h5 to commit message. Changes in v3: - Add "h3:" to commit message. arch/arm/boot/dts/sunxi-h3-h5.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 2494ea063cd4..6640ebfa6419 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -144,6 +144,19 @@ #size-cells = <0>; }; + usb_otg: usb@01c19000 { + compatible = "allwinner,sun8i-h3-musb"; + reg = <0x01c19000 0x400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = ; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + usbphy: phy@01c19400 { compatible = "allwinner,sun8i-h3-usb-phy"; reg = <0x01c19400 0x2c>, @@ -176,6 +189,25 @@ #phy-cells = <1>; }; + ehci0: usb@01c1a000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + status = "disabled"; + }; + + ohci0: usb@01c1a400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + status = "disabled"; + }; + ehci1: usb@01c1b000 { compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; reg = <0x01c1b000 0x100>;