From patchwork Thu Apr 20 19:05:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 9691165 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6E5376037F for ; Thu, 20 Apr 2017 19:06:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5B3A82621B for ; Thu, 20 Apr 2017 19:06:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4FB40284DD; Thu, 20 Apr 2017 19:06:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DB9F52621B for ; Thu, 20 Apr 2017 19:06:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=UDEuoVVPHW7l6gmG7iUirn8jIl0IvAssjmDD4f2vMFE=; b=jT3Eo0N6YKAHOsIjaju7KbSxsN +4tNEf5ZldwueTWPbI7+EJ9EFfMfJsjExpGC7q9Jht1t2JlPVQ6wB/qjHwVodbmO63VaJVCbARnMg wgUjnOiGcjIrUq64fxXrRPB+2bBnqXd4VZPTxvMAAdoTTN2HMlIo3rYhL7N2St0GCIsr2XswtPTo3 mEUoaQO09J8zXZC3dt2rMuWOlD59Iwg+500BwEpFc3baYNWSu/DbIiD83qF8Tmj9GDDLjXGA5EM97 O7sdooNZo8UPjY9y8YO0GxT8HQRIdZwkj3/a5ziyG07lglsrEbZY21W3j1mOm/fD2XVSOFE1AIW5g Z1k3l/6A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1d1HPX-0003yC-VR; Thu, 20 Apr 2017 19:06:35 +0000 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1d1HPI-0003et-8s for linux-arm-kernel@lists.infradead.org; Thu, 20 Apr 2017 19:06:22 +0000 Received: by mail-wm0-x244.google.com with SMTP id z129so184735wmb.1 for ; Thu, 20 Apr 2017 12:05:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SQmHOD7Ouz4YvSzJmDOQ8TtXVsmFk70xvkgscF2aT8k=; b=P04HM8RFVv7kdEMzff02PMipJHWryz56BI9EuFBF60NwVVHOMWwUFZpF5pqqVIExjz UD1PQ3bqJe4i694cyLCsd5oQnI6MXlIKb6E9UuS5aNaEZQswSt6EjOrwpB6bydeRVLMA 5JIaZduQ6XOxnOYY/HBGVYg15j4/PXxK5TMJFlvOO6bOklqllccDcB+durbcI6C5dGOP j/ApVpzsTxiom2PSO0zlOZT2nKCaScuStQDAtJWMH6qDtEcebMjQG6LOB54n2g8FrnlC KlfJo5cLBRPvOvG9zfCTNdGqwqnkrai/WEj5mHgwcRWFmgwfgRK2Y8kbqJouCvoLHGnS bjmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SQmHOD7Ouz4YvSzJmDOQ8TtXVsmFk70xvkgscF2aT8k=; b=ts+4v2qNgO6dbcceZZHN0ky2HzKdRn9fH5KLgtejEaJE34AoBCJC/i4pqWnGIjt0qn Wm/1hd3CLMW/IEENrDhCAxuNa1q0FV68GJ9yMlw8UmbUvrbJgum+budYkWuRFSgA+9NR OxvjcRskl/XlXlSSO2IfqLxpwbAYV69Bv7nQmotEGyy6/xX40cmbmOxgVe0sjzefuQq+ sfTpQ+zZ5rBTI0NfgGiP89956dsRLiKmrI2jHzDQbqB4UQ4aSjT8Yrni6MxtGjgmbapX UuNLYT3+SbyGCnhPM8i3DPSYq67J2VFKc1GCHJbnpwsJo+ltfCGVPWbxduXrk1RV7ccw 1bJQ== X-Gm-Message-State: AN3rC/7fhrguUyPdW9vmYrtxJ9IeLSxMZXLVVEcNzqy6K/DmWr67WAUx 9bJZobSDiC+DCw== X-Received: by 10.28.95.85 with SMTP id t82mr4718300wmb.3.1492715157614; Thu, 20 Apr 2017 12:05:57 -0700 (PDT) Received: from fainelli-desktop.irv.broadcom.com ([192.19.255.250]) by smtp.gmail.com with ESMTPSA id w126sm31487wmb.25.2017.04.20.12.05.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Apr 2017 12:05:56 -0700 (PDT) From: Florian Fainelli To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2] arm64: perf: Wire-up Cortex A53 L2 cache events and DTLB refills Date: Thu, 20 Apr 2017 12:05:44 -0700 Message-Id: <20170420190546.7453-2-f.fainelli@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170420190546.7453-1-f.fainelli@gmail.com> References: <20170420190546.7453-1-f.fainelli@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170420_120620_571935_9807165E X-CRM114-Status: UNSURE ( 9.56 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , opendmb@gmail.com, Peter Zijlstra , Catalin Marinas , alcooperx@gmail.com, Will Deacon , "open list:PERFORMANCE EVENTS SUBSYSTEM" , Arnaldo Carvalho de Melo , Alexander Shishkin , Florian Fainelli , Ingo Molnar MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add missing L2 cache events: read/write accesses and misses, as well as the DTLB refills. Signed-off-by: Florian Fainelli --- arch/arm64/kernel/perf_event.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 57ae9d9ed9bb..4f011cdd756d 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -290,6 +290,12 @@ static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE, [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL, + [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE, + [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL, + [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE, + [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL, + + [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL, [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL, [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,