From patchwork Thu Apr 20 19:05:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 9691171 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C16526037F for ; Thu, 20 Apr 2017 19:06:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AC12A284DD for ; Thu, 20 Apr 2017 19:06:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9D7592621B; Thu, 20 Apr 2017 19:06:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3263A2621B for ; Thu, 20 Apr 2017 19:06:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=0PVTORgGMfF90DV1uMtVTiDYiCkTp2ppccAlI795sTs=; b=FQ5IxjcXGoD7Vpo1+khk6l84z0 mBzNlvyoWlultwmA84x2Wd19QFS3MDnhCzAMn8qW7A+RTUHhU1/JSdWAgh2MXSqteqN7/DzOdUih3 9s2PdOYo/YrSCTYjvNXxjjMuzIIxq5bU2hwMSTKYBZZDkO8z94BftBYpMvNM/24HAj5tIqTUjvgtP YMtiPmfg6yAzNQZPI8kVEJ/h46HZqVQznNsRBIudpCYn2ttwBwZwmhvwSmWiPDcCk7/UgUE8WgrM/ U5+7z8/fV17kYMZcBDJRuoGYWtaMs5PINmtOy47PdWm7RYZwoJVAdQE3SAgZiodyurVZHYlho1LeH +l5uUhiQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1d1HPu-0004Tc-8z; Thu, 20 Apr 2017 19:06:58 +0000 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1d1HPM-0003fD-11 for linux-arm-kernel@lists.infradead.org; Thu, 20 Apr 2017 19:06:27 +0000 Received: by mail-wm0-x244.google.com with SMTP id o81so192741wmb.0 for ; Thu, 20 Apr 2017 12:06:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qqIeX8RXhTojnsf1zERvjk7bn3hHGyM8uUeNdPe5rzM=; b=hi5BCkgN/eT3j89LGT0IpHRe7pq51CjVdIEWnpYSYWb/Frq4vbXSKW2r9YDh5a68IX cm4MRAK+sEh6FhhmvzfkZUuat05FSbD6/GqmbgdrAGMhaNQoN+gMSo9Zsw3xY5H+zzQo Evk1LRJD3xo731plK4gEAWG49ChMBGPMIsuvHAaoeAWVKjzzFgwEQtsHrWiMJipeUKYA gGao/91eeSbO7GKqocqp8IrnAhlEjpA021LUxS+CRzYFag2Lihj5aDyXWpAVRZiknAhN 3pjatnRPn9tY3jlszf17HSJH+KVdWD8VhPIq/9SnNHc8DLEH9MixpjarwyDWO/befGj2 Tm2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qqIeX8RXhTojnsf1zERvjk7bn3hHGyM8uUeNdPe5rzM=; b=RY8cNm5J9Z0kmGwKwz/eNP8bvi9fe9SXfQ6z4koDt1VJxlypolVY4U/8jMfE2vieS0 TuRXtKf6KDH0XJVfXKxmyK5vooxAKYEEwVYTv8CILhhdh7AT0NvweAURt7emvYOQXvEp MZtLutBQccLI8xAZQ645P2htmca2T8/XeNbyRwRgiluTTJDTADvDYj8GbvhzZMnROBmV MTcTLwWcP2xKqNaIE1NiyXoFe2eoK+/NjVQa0UXCWJMN+rFpIpyLYF9dWC9ad0n+rJKs 7mt8DsC5JO87ehZfPqW6cKk9zoU+YzqecEJGJhBBsw33sCblaxs001aLe2WfYsk5X7g2 H3ZQ== X-Gm-Message-State: AN3rC/6J44/LJK66MnRfeKcB+4R7nUyGBBwllMcOyHdyDfIKRCkOACv0 WbqzFqCsn8qVqw== X-Received: by 10.28.104.195 with SMTP id d186mr4653011wmc.111.1492715164062; Thu, 20 Apr 2017 12:06:04 -0700 (PDT) Received: from fainelli-desktop.irv.broadcom.com ([192.19.255.250]) by smtp.gmail.com with ESMTPSA id w126sm31487wmb.25.2017.04.20.12.06.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Apr 2017 12:06:03 -0700 (PDT) From: Florian Fainelli To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 Date: Thu, 20 Apr 2017 12:05:46 -0700 Message-Id: <20170420190546.7453-4-f.fainelli@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170420190546.7453-1-f.fainelli@gmail.com> References: <20170420190546.7453-1-f.fainelli@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170420_120624_614939_8FFE355F X-CRM114-Status: GOOD ( 10.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , opendmb@gmail.com, Peter Zijlstra , Catalin Marinas , alcooperx@gmail.com, Will Deacon , "open list:PERFORMANCE EVENTS SUBSYSTEM" , Arnaldo Carvalho de Melo , Alexander Shishkin , Florian Fainelli , Ingo Molnar MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The ARMv8 PMUv3 cache map did not include the L2 cache events, add them. Signed-off-by: Florian Fainelli --- arch/arm64/kernel/perf_event.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 4f011cdd756d..a664c575f3fd 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -264,6 +264,11 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE, [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL, + [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE, + [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL, + [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE, + [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL, + [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL, [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,