| Message ID | 20170524111724.28431-1-icenowy@aosc.io (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, May 24, 2017 at 7:17 PM, Icenowy Zheng <icenowy@aosc.io> wrote: > Allwinner V3s SoC features a "Display Engine 2.0" with only one mixer > and only one TCON connected to this mixer, which have RGB LCD output. > > Add device nodes for this display pipeline. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > arch/arm/boot/dts/sun8i-v3s.dtsi | 83 ++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 83 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi > index a49ebef53c91..3a06dc5b3746 100644 > --- a/arch/arm/boot/dts/sun8i-v3s.dtsi > +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi > @@ -61,6 +61,12 @@ > }; > }; > > + de: display-engine { > + compatible = "allwinner,sun8i-v3s-display-engine"; > + allwinner,pipelines = <&mixer0>; > + status = "disabled"; > + }; > + > timer { > compatible = "arm,armv7-timer"; > interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > @@ -95,6 +101,83 @@ > #size-cells = <1>; > ranges; > > + display_clocks: clock@1000000 { > + compatible = "allwinner,sun8i-v3s-de2-clk"; > + reg = <0x01000000 0x100000>; > + clocks = <&ccu CLK_DE>, > + <&ccu CLK_BUS_DE>; > + clock-names = "mod", > + "bus"; > + resets = <&ccu RST_BUS_DE>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + mixer0: mixer@1100000 { Since there's only one, can you drop the numbering suffix? Same with the TCON. > + compatible = "allwinner,sun8i-v3s-de2-mixer"; > + reg = <0x01100000 0x100000>; The display engine also has an interrupt. Please list it. ChenYu
于 2017年5月25日 GMT+08:00 下午4:37:31, Chen-Yu Tsai <wens@csie.org> 写到: >On Wed, May 24, 2017 at 7:17 PM, Icenowy Zheng <icenowy@aosc.io> wrote: >> Allwinner V3s SoC features a "Display Engine 2.0" with only one mixer >> and only one TCON connected to this mixer, which have RGB LCD output. >> >> Add device nodes for this display pipeline. >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >> --- >> arch/arm/boot/dts/sun8i-v3s.dtsi | 83 >++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 83 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi >b/arch/arm/boot/dts/sun8i-v3s.dtsi >> index a49ebef53c91..3a06dc5b3746 100644 >> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi >> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi >> @@ -61,6 +61,12 @@ >> }; >> }; >> >> + de: display-engine { >> + compatible = "allwinner,sun8i-v3s-display-engine"; >> + allwinner,pipelines = <&mixer0>; >> + status = "disabled"; >> + }; >> + >> timer { >> compatible = "arm,armv7-timer"; >> interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | >IRQ_TYPE_LEVEL_LOW)>, >> @@ -95,6 +101,83 @@ >> #size-cells = <1>; >> ranges; >> >> + display_clocks: clock@1000000 { >> + compatible = "allwinner,sun8i-v3s-de2-clk"; >> + reg = <0x01000000 0x100000>; >> + clocks = <&ccu CLK_DE>, >> + <&ccu CLK_BUS_DE>; >> + clock-names = "mod", >> + "bus"; >> + resets = <&ccu RST_BUS_DE>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + }; >> + >> + mixer0: mixer@1100000 { > >Since there's only one, can you drop the numbering suffix? >Same with the TCON. I just want to keep the consistency with dual-pipeline SoCs. (H3, A64, H5, etc) However, if dropping it is better, I will drop it -- I think usually for things that is available for multiple on some SoCs and single on others, we keep the 0 in node name... > >> + compatible = "allwinner,sun8i-v3s-de2-mixer"; >> + reg = <0x01100000 0x100000>; > >The display engine also has an interrupt. Please list it It's a overall interrupt for DE2, not mixer interrupt. I will add it after we have proper interrupt chaining facility for DE2. It cannot fit here in mixer node. > >ChenYu
On Thu, May 25, 2017 at 9:54 PM, Icenowy Zheng <icenowy@aosc.io> wrote: > > > 于 2017年5月25日 GMT+08:00 下午4:37:31, Chen-Yu Tsai <wens@csie.org> 写到: >>On Wed, May 24, 2017 at 7:17 PM, Icenowy Zheng <icenowy@aosc.io> wrote: >>> Allwinner V3s SoC features a "Display Engine 2.0" with only one mixer >>> and only one TCON connected to this mixer, which have RGB LCD output. >>> >>> Add device nodes for this display pipeline. >>> >>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >>> --- >>> arch/arm/boot/dts/sun8i-v3s.dtsi | 83 >>++++++++++++++++++++++++++++++++++++++++ >>> 1 file changed, 83 insertions(+) >>> >>> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi >>b/arch/arm/boot/dts/sun8i-v3s.dtsi >>> index a49ebef53c91..3a06dc5b3746 100644 >>> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi >>> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi >>> @@ -61,6 +61,12 @@ >>> }; >>> }; >>> >>> + de: display-engine { >>> + compatible = "allwinner,sun8i-v3s-display-engine"; >>> + allwinner,pipelines = <&mixer0>; >>> + status = "disabled"; >>> + }; >>> + >>> timer { >>> compatible = "arm,armv7-timer"; >>> interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | >>IRQ_TYPE_LEVEL_LOW)>, >>> @@ -95,6 +101,83 @@ >>> #size-cells = <1>; >>> ranges; >>> >>> + display_clocks: clock@1000000 { >>> + compatible = "allwinner,sun8i-v3s-de2-clk"; >>> + reg = <0x01000000 0x100000>; >>> + clocks = <&ccu CLK_DE>, >>> + <&ccu CLK_BUS_DE>; >>> + clock-names = "mod", >>> + "bus"; >>> + resets = <&ccu RST_BUS_DE>; >>> + #clock-cells = <1>; >>> + #reset-cells = <1>; >>> + }; >>> + >>> + mixer0: mixer@1100000 { >> >>Since there's only one, can you drop the numbering suffix? >>Same with the TCON. > > I just want to keep the consistency with dual-pipeline SoCs. (H3, A64, H5, etc) > > However, if dropping it is better, I will drop it -- I think usually for things > that is available for multiple on some SoCs and single on others, > we keep the 0 in node name... You might want that if you were going to include it in another SoC's dtsi file, such as the situation with A23/A33. However that is not the case here. Moreover, the datasheet lists them without the number. > >> >>> + compatible = "allwinner,sun8i-v3s-de2-mixer"; >>> + reg = <0x01100000 0x100000>; >> >>The display engine also has an interrupt. Please list it > > It's a overall interrupt for DE2, not mixer interrupt. > > I will add it after we have proper interrupt chaining facility for DE2. > > It cannot fit here in mixer node. Could you elaborate? If it is just shared, then listing it several times is OK. If the interrupt registers are not in this address space, then I agree, it needs to be dealt with separately and not added here. However some thought should be given about how the device tree binding should be. ChenYu > >> >>ChenYu > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. > For more options, visit https://groups.google.com/d/optout.
于 2017年5月25日 GMT+08:00 下午10:20:33, Chen-Yu Tsai <wens@csie.org> 写到: >On Thu, May 25, 2017 at 9:54 PM, Icenowy Zheng <icenowy@aosc.io> wrote: >> >> >> 于 2017年5月25日 GMT+08:00 下午4:37:31, Chen-Yu Tsai <wens@csie.org> 写到: >>>On Wed, May 24, 2017 at 7:17 PM, Icenowy Zheng <icenowy@aosc.io> >wrote: >>>> Allwinner V3s SoC features a "Display Engine 2.0" with only one >mixer >>>> and only one TCON connected to this mixer, which have RGB LCD >output. >>>> >>>> Add device nodes for this display pipeline. >>>> >>>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >>>> --- >>>> arch/arm/boot/dts/sun8i-v3s.dtsi | 83 >>>++++++++++++++++++++++++++++++++++++++++ >>>> 1 file changed, 83 insertions(+) >>>> >>>> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi >>>b/arch/arm/boot/dts/sun8i-v3s.dtsi >>>> index a49ebef53c91..3a06dc5b3746 100644 >>>> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi >>>> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi >>>> @@ -61,6 +61,12 @@ >>>> }; >>>> }; >>>> >>>> + de: display-engine { >>>> + compatible = "allwinner,sun8i-v3s-display-engine"; >>>> + allwinner,pipelines = <&mixer0>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> timer { >>>> compatible = "arm,armv7-timer"; >>>> interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | >>>IRQ_TYPE_LEVEL_LOW)>, >>>> @@ -95,6 +101,83 @@ >>>> #size-cells = <1>; >>>> ranges; >>>> >>>> + display_clocks: clock@1000000 { >>>> + compatible = "allwinner,sun8i-v3s-de2-clk"; >>>> + reg = <0x01000000 0x100000>; >>>> + clocks = <&ccu CLK_DE>, >>>> + <&ccu CLK_BUS_DE>; >>>> + clock-names = "mod", >>>> + "bus"; >>>> + resets = <&ccu RST_BUS_DE>; >>>> + #clock-cells = <1>; >>>> + #reset-cells = <1>; >>>> + }; >>>> + >>>> + mixer0: mixer@1100000 { >>> >>>Since there's only one, can you drop the numbering suffix? >>>Same with the TCON. >> >> I just want to keep the consistency with dual-pipeline SoCs. (H3, >A64, H5, etc) >> >> However, if dropping it is better, I will drop it -- I think usually >for things >> that is available for multiple on some SoCs and single on others, >> we keep the 0 in node name... > >You might want that if you were going to include it in another SoC's >dtsi >file, such as the situation with A23/A33. However that is not the case >here. >Moreover, the datasheet lists them without the number. OK... > >> >>> >>>> + compatible = >"allwinner,sun8i-v3s-de2-mixer"; >>>> + reg = <0x01100000 0x100000>; >>> >>>The display engine also has an interrupt. Please list it >> >> It's a overall interrupt for DE2, not mixer interrupt. >> >> I will add it after we have proper interrupt chaining facility for >DE2. >> >> It cannot fit here in mixer node. > >Could you elaborate? If it is just shared, then listing it several >times >is OK. If the interrupt registers are not in this address space, then The interrupt dealing code is still not so clear, and totally not present in BSP DE2 code (the BSP just didn't use the interrupt). We doesn't even know where the interrupt register is, and we cannot promise it's not broken (as their is even no application of it in BSP). So it couldn't be added now. >I agree, it needs to be dealt with separately and not added here. >However >some thought should be given about how the device tree binding should >be. > >ChenYu > >> >>> >>>ChenYu >> >> -- >> You received this message because you are subscribed to the Google >Groups "linux-sunxi" group. >> To unsubscribe from this group and stop receiving emails from it, >send an email to linux-sunxi+unsubscribe@googlegroups.com. >> For more options, visit https://groups.google.com/d/optout.
On Thu, May 25, 2017 at 10:28:24PM +0800, Icenowy Zheng wrote: > >>>> + compatible = "allwinner,sun8i-v3s-de2-mixer"; > >>>> + reg = <0x01100000 0x100000>; > >>> > >>>The display engine also has an interrupt. Please list it > >> > >> It's a overall interrupt for DE2, not mixer interrupt. > >> > >> I will add it after we have proper interrupt chaining facility > >> for DE2. > >> > >> It cannot fit here in mixer node. > > > > Could you elaborate? If it is just shared, then listing it several > > times is OK. If the interrupt registers are not in this address > > space, then > > The interrupt dealing code is still not so clear, and totally not > present in BSP DE2 code (the BSP just didn't use the interrupt). > > We doesn't even know where the interrupt register is, and we cannot > promise it's not broken (as their is even no application of it in BSP). Whether it's broken or not is out of the question here. Adding it later would either break the DT compatibility, or introduce a crippled driver for users that do not have a recent enough DT. None of the two are really acceptable. Especially if your plan is to add support for these. Maxime
在 2017-05-29 16:59，Maxime Ripard 写道： > On Thu, May 25, 2017 at 10:28:24PM +0800, Icenowy Zheng wrote: >> >>>> + compatible = "allwinner,sun8i-v3s-de2-mixer"; >> >>>> + reg = <0x01100000 0x100000>; >> >>> >> >>>The display engine also has an interrupt. Please list it >> >> >> >> It's a overall interrupt for DE2, not mixer interrupt. >> >> >> >> I will add it after we have proper interrupt chaining facility >> >> for DE2. >> >> >> >> It cannot fit here in mixer node. >> > >> > Could you elaborate? If it is just shared, then listing it several >> > times is OK. If the interrupt registers are not in this address >> > space, then >> >> The interrupt dealing code is still not so clear, and totally not >> present in BSP DE2 code (the BSP just didn't use the interrupt). >> >> We doesn't even know where the interrupt register is, and we cannot >> promise it's not broken (as their is even no application of it in >> BSP). > > Whether it's broken or not is out of the question here. Adding it > later would either break the DT compatibility, or introduce a crippled > driver for users that do not have a recent enough DT. None of the two > are really acceptable. > > Especially if your plan is to add support for these. I have no such plan -- even the BSP driver doesn't use the IRQ at all. > > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com
On Mon, May 29, 2017 at 09:01:59PM +0800, icenowy@aosc.io wrote: > 在 2017-05-29 16:59，Maxime Ripard 写道： > > On Thu, May 25, 2017 at 10:28:24PM +0800, Icenowy Zheng wrote: > > > >>>> + compatible = "allwinner,sun8i-v3s-de2-mixer"; > > > >>>> + reg = <0x01100000 0x100000>; > > > >>> > > > >>>The display engine also has an interrupt. Please list it > > > >> > > > >> It's a overall interrupt for DE2, not mixer interrupt. > > > >> > > > >> I will add it after we have proper interrupt chaining facility > > > >> for DE2. > > > >> > > > >> It cannot fit here in mixer node. > > > > > > > > Could you elaborate? If it is just shared, then listing it several > > > > times is OK. If the interrupt registers are not in this address > > > > space, then > > > > > > The interrupt dealing code is still not so clear, and totally not > > > present in BSP DE2 code (the BSP just didn't use the interrupt). > > > > > > We doesn't even know where the interrupt register is, and we cannot > > > promise it's not broken (as their is even no application of it in > > > BSP). > > > > Whether it's broken or not is out of the question here. Adding it > > later would either break the DT compatibility, or introduce a crippled > > driver for users that do not have a recent enough DT. None of the two > > are really acceptable. > > > > Especially if your plan is to add support for these. > > I have no such plan -- even the BSP driver doesn't use the IRQ at all. We'll see how it turns out.. I applied that patch. Maxime
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index a49ebef53c91..3a06dc5b3746 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -61,6 +61,12 @@ }; }; + de: display-engine { + compatible = "allwinner,sun8i-v3s-display-engine"; + allwinner,pipelines = <&mixer0>; + status = "disabled"; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -95,6 +101,83 @@ #size-cells = <1>; ranges; + display_clocks: clock@1000000 { + compatible = "allwinner,sun8i-v3s-de2-clk"; + reg = <0x01000000 0x100000>; + clocks = <&ccu CLK_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-v3s-de2-mixer"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks 0>, + <&display_clocks 6>; + clock-names = "bus", + "mod"; + resets = <&display_clocks 0>; + assigned-clocks = <&display_clocks 6>; + assigned-clock-rates = <150000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mixer0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_mixer0>; + }; + }; + }; + }; + + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun8i-v3s-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_TCON0>, + <&ccu CLK_TCON0>; + clock-names = "ahb", + "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_TCON0>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + mmc0: mmc@01c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>;
Allwinner V3s SoC features a "Display Engine 2.0" with only one mixer and only one TCON connected to this mixer, which have RGB LCD output. Add device nodes for this display pipeline. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- arch/arm/boot/dts/sun8i-v3s.dtsi | 83 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+)