From patchwork Wed May 31 14:32:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 9757413 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EB90F60360 for ; Wed, 31 May 2017 14:35:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DB35C26E78 for ; Wed, 31 May 2017 14:35:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CF16428420; Wed, 31 May 2017 14:35:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 54E9626E78 for ; Wed, 31 May 2017 14:35:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IzL/QjUfPrNFhuTbNviF8Q1YmUIvLIhIJXR3k2FubFw=; b=P9wGcKatZ4szEc CP71huix3mxZWX6avcmo3r5VvCI3Dqj+QuokTo8Y72WH2O1ceZLhflUcTJiyMTQv7Icx4YXx5DehU Rm+k9YBSzXUmMY6b7qg+dOvQ652h5R1f2qtO5kNHa+7jRHvMjxLufxSQX1zqhWediPGsE1qkajJar Vf65T0LkFbDN/ZraOIdJFfE4AfjyJcoeyAFO4Cl/obuygpAx1jYKWhrWLBQ+AarjnZpA+3wDDWiqW YDYPJ4dwFNnZ1TiizeIduwL1DjXj4+EUv5VsTVEi2yb7DIBPRJpMLRD7kxK60BaU5d1vfcETkT9eY +F+RjVfyQKK7Tq0jO+iw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dG4iJ-00030N-Pq; Wed, 31 May 2017 14:35:07 +0000 Received: from szxga03-in.huawei.com ([45.249.212.189]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dG4hr-000248-MF for linux-arm-kernel@lists.infradead.org; Wed, 31 May 2017 14:34:47 +0000 Received: from 172.30.72.54 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.54]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOP20893; Wed, 31 May 2017 22:34:05 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Wed, 31 May 2017 22:33:55 +0800 From: shameer To: , , , , , Subject: [RFCv2 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Date: Wed, 31 May 2017 15:32:13 +0100 Message-ID: <20170531143213.82100-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170531143213.82100-1-shameerali.kolothum.thodi@huawei.com> References: <20170531143213.82100-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.592ED45E.001A, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 3353111ed35acc79e0a3f0c2ea9bec25 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170531_073443_166118_8921C65A X-CRM114-Status: GOOD ( 13.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gabriele.paoloni@huawei.com, john.garry@huawei.com, linuxarm@huawei.com, shameer , linux-acpi@vger.kernel.org, iommu@lists.linux-foundation.org, wangzhou1@hisilicon.com, guohanjun@huawei.com, linux-arm-kernel@lists.infradead.org, devel@acpica.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a ACPI table based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. The HW ITS address region associated with the dev is retrieved using a new helper function added in the IORT code. Signed-off-by: shameer --- drivers/iommu/arm-smmu-v3.c | 49 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 46 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index abe4b88..3767526 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -597,6 +597,7 @@ struct arm_smmu_device { u32 features; #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) +#define ARM_SMMU_OPT_RESV_HW_MSI (1 << 1) u32 options; struct arm_smmu_cmdq cmdq; @@ -1755,6 +1756,38 @@ static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid) static struct iommu_ops arm_smmu_ops; +#ifdef CONFIG_ACPI +static struct iommu_resv_region *arm_smmu_acpi_alloc_hw_msi(struct device *dev) +{ + struct iommu_resv_region *region; + struct irq_domain *irq_dom; + int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + u64 base; + + irq_dom = pci_msi_get_device_domain(to_pci_dev(dev)); + if (irq_dom) { + int ret; + u32 rid; + + rid = pci_msi_domain_get_msi_rid(irq_dom, to_pci_dev(dev)); + ret = iort_dev_find_its_base(dev, rid, 0, &base); + if (!ret) { + dev_info(dev, "SMMUv3:HW MSI resv addr 0x%pa\n", &base); + region = iommu_alloc_resv_region(base, SZ_128K, + prot, IOMMU_RESV_MSI); + return region; + } + } + + return NULL; +} +#else +static struct iommu_resv_region *arm_smmu_acpi_alloc_hw_msi(struct device *dev) +{ + return NULL; +} +#endif + static int arm_smmu_add_device(struct device *dev) { int i, ret; @@ -1903,11 +1936,20 @@ static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args) static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { - struct iommu_resv_region *region; + struct iommu_fwspec *fwspec = dev->iommu_fwspec; + struct iommu_resv_region *region = NULL; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + struct arm_smmu_device *smmu; + + smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI); + if (smmu && (smmu->options & ARM_SMMU_OPT_RESV_HW_MSI) && + dev_is_pci(dev)) + region = arm_smmu_acpi_alloc_hw_msi(dev); + + if (!region) + region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, + prot, IOMMU_RESV_SW_MSI); if (!region) return; @@ -2611,6 +2653,7 @@ static void parse_driver_acpi_options(struct acpi_iort_smmu_v3 *iort_smmu, switch (iort_smmu->model) { case ACPI_IORT_SMMU_HISILICON_HI161X: smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; + smmu->options |= ARM_SMMU_OPT_RESV_HW_MSI; break; default: break;