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Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by merlin.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dI2nF-0004YI-8t for linux-arm-kernel@lists.infradead.org; Tue, 06 Jun 2017 00:56:23 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 68C83ADE4; Tue, 6 Jun 2017 00:55:24 +0000 (UTC) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 28/28] ARM: owl: smp: Implement SPS power-gating for CPU2 and CPU3 Date: Tue, 6 Jun 2017 02:54:26 +0200 Message-Id: <20170606005426.26446-29-afaerber@suse.de> X-Mailer: git-send-email 2.12.3 In-Reply-To: <20170606005426.26446-1-afaerber@suse.de> References: <20170606005426.26446-1-afaerber@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170605_205621_627684_29752E3D X-CRM114-Status: GOOD ( 16.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: support@lemaker.org, =?UTF-8?q?=E5=BC=A0=E5=A4=A9=E7=9B=8A?= , 96boards@ucrobotics.com, linux-kernel@vger.kernel.org, Thomas Liau , Russell King , mp-cs@actions-semi.com, =?UTF-8?q?=E5=88=98=E7=82=9C?= , =?UTF-8?q?Andreas=20F=C3=A4rber?= , =?UTF-8?q?=E5=BC=A0=E4=B8=9C=E9=A3=8E?= Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Bring up the two remaining CPUs by calling into PM domain code. Signed-off-by: Andreas Färber --- v3 -> v4: * Reused PM domain helper code to avoid code duplication v3: new arch/arm/mach-actions/Kconfig | 1 + arch/arm/mach-actions/platsmp.c | 36 ++++++++++++++++++++++++++++++++++-- 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-actions/Kconfig b/arch/arm/mach-actions/Kconfig index 717adc1630a1..ad9c5c89c683 100644 --- a/arch/arm/mach-actions/Kconfig +++ b/arch/arm/mach-actions/Kconfig @@ -10,6 +10,7 @@ menuconfig ARCH_ACTIONS select GENERIC_IRQ_CHIP select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP + select OWL_PM_DOMAINS_HELPER select OWL_TIMER help This enables support for the Actions Semiconductor S500 SoC family. diff --git a/arch/arm/mach-actions/platsmp.c b/arch/arm/mach-actions/platsmp.c index 9d3601ebe535..b4806ce0e9bb 100644 --- a/arch/arm/mach-actions/platsmp.c +++ b/arch/arm/mach-actions/platsmp.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -28,7 +29,13 @@ #define OWL_CPUx_FLAG_BOOT 0x55aa +#define OWL_SPS_PG_CTL_PWR_CPU2 BIT(5) +#define OWL_SPS_PG_CTL_PWR_CPU3 BIT(6) +#define OWL_SPS_PG_CTL_ACK_CPU2 BIT(21) +#define OWL_SPS_PG_CTL_ACK_CPU3 BIT(22) + static void __iomem *scu_base_addr; +static void __iomem *sps_base_addr; static void __iomem *timer_base_addr; static int ncores; @@ -58,14 +65,27 @@ void owl_secondary_startup(void); static int s500_wakeup_secondary(unsigned int cpu) { + int ret; + if (cpu > 3) return -EINVAL; + /* The generic PM domain driver is not available this early. */ switch (cpu) { case 2: + ret = owl_sps_set_pg(sps_base_addr, + OWL_SPS_PG_CTL_PWR_CPU2, + OWL_SPS_PG_CTL_ACK_CPU2, true); + if (ret) + return ret; + break; case 3: - /* CPU2/3 are power-gated */ - return -EINVAL; + ret = owl_sps_set_pg(sps_base_addr, + OWL_SPS_PG_CTL_PWR_CPU3, + OWL_SPS_PG_CTL_ACK_CPU3, true); + if (ret) + return ret; + break; } /* wait for CPUx to run to WFE instruction */ @@ -133,6 +153,18 @@ static void __init s500_smp_prepare_cpus(unsigned int max_cpus) return; } + node = of_find_compatible_node(NULL, NULL, "actions,s500-sps"); + if (!node) { + pr_err("%s: missing sps\n", __func__); + return; + } + + sps_base_addr = of_iomap(node, 0); + if (!sps_base_addr) { + pr_err("%s: could not map sps registers\n", __func__); + return; + } + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); if (!node) {