From patchwork Fri Jul 14 06:42:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 9839967 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 300D6602D8 for ; Fri, 14 Jul 2017 06:43:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1F1D828763 for ; Fri, 14 Jul 2017 06:43:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 13B4A2877F; Fri, 14 Jul 2017 06:43:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 91B5128763 for ; Fri, 14 Jul 2017 06:43:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=x+AT6PuUvbkNjG3J6tAUQbB+XYfgLN/J7na0lANlnZo=; b=r3zfqOAAA3GPKzvaYt6yTMfJ3W uqCBlsk+PkjoC2IgOQrcelUC+DkHrg61QommuQeozAFt9VGxi5Fch+8VomxCp6wdYIlo/fA9DbA9l PZSUai5eh7p5tVabjBKcmaCr4mmACrjVRot5i+EdKktMnLeIiX8ANVuUbs37Wcd4cfhtZynDRfvHx 2WG346ZsOQ4no7nw+MlnKNHe782CWMXBe3j9QmgVmPO3/zyj1ya0JYM8DzH0oTTB0FxsIfEbi53gM ErpFVlFjZDtxYu1akwkc8Ola7Ty76But8HJigT9Zd9OYNiXrcsdehvaS0gq+Iz40cmJTVMyGfWY2C sOOM+YbA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dVuKN-0006QC-J2; Fri, 14 Jul 2017 06:43:51 +0000 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76] helo=wens.csie.org) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dVuK6-00069m-48 for linux-arm-kernel@lists.infradead.org; Fri, 14 Jul 2017 06:43:36 +0000 Received: by wens.csie.org (Postfix, from userid 1000) id 112C65FE94; Fri, 14 Jul 2017 14:43:08 +0800 (CST) From: Chen-Yu Tsai To: Maxime Ripard , Ulf Hansson , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland Subject: [PATCH 03/11] clk: sunxi-ng: a83t: Support new timing mode for mmc2 clock Date: Fri, 14 Jul 2017 14:42:54 +0800 Message-Id: <20170714064302.20383-4-wens@csie.org> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20170714064302.20383-1-wens@csie.org> References: <20170714064302.20383-1-wens@csie.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170713_234334_355270_EE5FAB0A X-CRM114-Status: UNSURE ( 9.81 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Chen-Yu Tsai , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The MMC2 clock supports a new timing mode. When the new mode is active, the output clock rate is halved. This patch sets the feature flag for the new timing mode, and adds a pre-divider based on the mode bit. Signed-off-by: Chen-Yu Tsai --- drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 38 +++++++++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c index 947f9f6e05d2..ee6688e9b361 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c @@ -418,14 +418,36 @@ static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1", static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1", 0x08c, 8, 3, 0); -/* TODO Support MMC2 clock's new timing mode. */ -static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, - 0x090, - 0, 4, /* M */ - 16, 2, /* P */ - 24, 2, /* mux */ - BIT(31), /* gate */ - 0); +/* + * MMC2 supports both old and new timing modes. When the new timing + * mode is active, the output clock rate is halved by two. Here we + * treat it as a variable pre-divider. Note that the pre-divider is + * _not_ included in the possible factors during a set clock rate + * operation. It is only read out. + */ +static const struct ccu_mux_var_prediv mmc2_new_timing_predivs[] = { + { .index = 0, .shift = 30, .width = 1 }, + { .index = 1, .shift = 30, .width = 1 }, +}; +static struct ccu_mp mmc2_clk = { + .enable = BIT(31), + .m = _SUNXI_CCU_DIV(0, 4), + .p = _SUNXI_CCU_DIV(16, 2), + .mux = { + .shift = 24, + .width = 2, + .var_predivs = mmc2_new_timing_predivs, + .n_var_predivs = ARRAY_SIZE(mmc2_new_timing_predivs), + }, + .common = { + .reg = 0x090, + .features = CCU_FEATURE_MMC_TIMING_SWITCH, + .hw.init = CLK_HW_INIT_PARENTS("mmc2", + mod0_default_parents, + &ccu_mp_ops, + CLK_GET_RATE_NOCACHE), + }, +}; static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2", 0x090, 20, 3, 0);