Message ID | 20170722064313.7535-1-codekipper@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Hi Marcus, On Sat, Jul 22, 2017 at 08:43:13AM +0200, codekipper@gmail.com wrote: > From: Marcus Cooper <codekipper@gmail.com> > > The A20 SoC has a couple of i2s blocks. This patch adds > the pinctrl settings for block i2s0. > > Signed-off-by: Marcus Cooper <codekipper@gmail.com> We're not adding pin groups that are not used by anyone. If you have a board using them, please send the DT for that board too. Thanks! Maxime
No...I've only got an Olimex SOM EVB which exposes these pins on a GPIO header (like many of the dev boards). Just thought if we included them in the dtsi then adding overlays for i2s devices would be simplified. BR, CK On 24 July 2017 at 10:20, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > Hi Marcus, > > On Sat, Jul 22, 2017 at 08:43:13AM +0200, codekipper@gmail.com wrote: >> From: Marcus Cooper <codekipper@gmail.com> >> >> The A20 SoC has a couple of i2s blocks. This patch adds >> the pinctrl settings for block i2s0. >> >> Signed-off-by: Marcus Cooper <codekipper@gmail.com> > > We're not adding pin groups that are not used by anyone. If you have a > board using them, please send the DT for that board too. > > Thanks! > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 96bee776e145..01f9ee329913 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -1163,6 +1163,31 @@ function = "i2c3"; }; + i2s0_mclk: i2s0@0 { + pins = "PB5"; + function = "i2s0"; + }; + + i2s0_bclk: i2s0@1 { + pins = "PB6"; + function = "i2s0"; + }; + + i2s0_lrclk: i2s0@2 { + pins = "PB7"; + function = "i2s0"; + }; + + i2s0_sdo0: i2s0@3 { + pins = "PB8"; + function = "i2s0"; + }; + + i2s0_sdi: i2s0@4 { + pins = "PB12"; + function = "i2s0"; + }; + ir0_rx_pins_a: ir0@0 { pins = "PB4"; function = "ir0";