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[91.5.97.1]) by smtp.googlemail.com with ESMTPSA id l143sm2043472wmg.46.2017.07.22.12.19.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 22 Jul 2017 12:20:00 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, khilman@baylibre.com, carlo@caione.org, linux@armlinux.org.uk Subject: [PATCH v4 2/7] ARM: smp_scu: add a helper for powering on a specific CPU Date: Sat, 22 Jul 2017 21:19:41 +0200 Message-Id: <20170722191946.22938-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170722191946.22938-1-martin.blumenstingl@googlemail.com> References: <20170722191946.22938-1-martin.blumenstingl@googlemail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170722_122022_755159_AC5B7E90 X-CRM114-Status: UNSURE ( 9.78 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, robh+dt@kernel.org, Martin Blumenstingl , arnd@arndb.de MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP To boot the secondary CPUs on the Amlogic Meson8/Meson8m2 (Cortex-A9) and Meson8b (Cortex-A5) SoCs we have to enable SCU mode SCU_PM_NORMAL, otherwise the secondary cores will not start. This patch adds a scu_cpu_power_enable() function which can be used to enable SCU_PM_NORMAL for a specific (logical) CPU. An internal helper function is also created, to avoid code duplication with scu_power_mode(). Signed-off-by: Martin Blumenstingl --- arch/arm/include/asm/smp_scu.h | 6 ++++++ arch/arm/kernel/smp_scu.c | 39 +++++++++++++++++++++++++++++---------- 2 files changed, 35 insertions(+), 10 deletions(-) diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h index bfe163c40024..11e636f33ed9 100644 --- a/arch/arm/include/asm/smp_scu.h +++ b/arch/arm/include/asm/smp_scu.h @@ -26,6 +26,7 @@ static inline unsigned long scu_a9_get_base(void) #ifdef CONFIG_HAVE_ARM_SCU unsigned int scu_get_core_count(void __iomem *); int scu_power_mode(void __iomem *, unsigned int); +int scu_cpu_power_enable(void __iomem *, unsigned int); #else static inline unsigned int scu_get_core_count(void __iomem *scu_base) { @@ -35,6 +36,11 @@ static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode) { return -EINVAL; } +static inline int scu_cpu_power_enable(void __iomem *scu_base, + unsigned int mode) +{ + return -EINVAL; +} #endif #if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU) diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c index 72f9241ad5db..ef09121b18eb 100644 --- a/arch/arm/kernel/smp_scu.c +++ b/arch/arm/kernel/smp_scu.c @@ -72,18 +72,12 @@ void scu_enable(void __iomem *scu_base) } #endif -/* - * Set the executing CPUs power mode as defined. This will be in - * preparation for it executing a WFI instruction. - * - * This function must be called with preemption disabled, and as it - * has the side effect of disabling coherency, caches must have been - * flushed. Interrupts must also have been disabled. - */ -int scu_power_mode(void __iomem *scu_base, unsigned int mode) +static int scu_set_power_mode_internal(void __iomem *scu_base, + unsigned int logical_cpu, + unsigned int mode) { unsigned int val; - int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); + int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0); if (mode > 3 || mode == 1 || cpu > 3) return -EINVAL; @@ -94,3 +88,28 @@ int scu_power_mode(void __iomem *scu_base, unsigned int mode) return 0; } + +/* + * Set the executing CPUs power mode as defined. This will be in + * preparation for it executing a WFI instruction. + * + * This function must be called with preemption disabled, and as it + * has the side effect of disabling coherency, caches must have been + * flushed. Interrupts must also have been disabled. + */ +int scu_power_mode(void __iomem *scu_base, unsigned int mode) +{ + return scu_set_power_mode_internal(scu_base, smp_processor_id(), mode); +} + +/* + * Set the executing CPUs power mode to SCU_PM_NORMAL. + * + * This function must be called with preemption disabled, and as it + * has the side effect of disabling coherency, caches must have been + * flushed. Interrupts must also have been disabled. + */ +int scu_cpu_power_enable(void __iomem *scu_base, unsigned int cpu) +{ + return scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL); +}