From patchwork Fri Jul 28 21:21:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 9869527 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9426B6037D for ; Fri, 28 Jul 2017 21:23:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7F4DA28564 for ; Fri, 28 Jul 2017 21:23:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 73F17288F6; Fri, 28 Jul 2017 21:23:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, DKIM_VALID, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EB2AD28564 for ; Fri, 28 Jul 2017 21:23:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=lz9sF9LFPbWt0NKDmVBSKoXtfZjqZgAGSAfVKgLu0xY=; b=DMlqIPuoElLpH2QGY3keojKrj3 iEYsdfxC1W+uu4HpBtVD/ZXdYCJYRdNayNzPSm9fFj7P0IR6CWTLr3hpWJyZBB00oEHj4q74rXBEw aDudmFScggbYvM8w//mupPu1AKRjwe2ep6loE7a4q706QVwO6sg78dF+EfFNVvS/RsF/IJ4v1wPD6 9xLK/cQEHbTwDnTISeHEvi2ksFhNQDkki5mdVfoyePXM6m7/c6awcTR5eQC6CgrMpNjamsdMoZUi9 G0hIZj/DyHRynbh2P4JQtWnRp2EgFRwfUsakM2IXIrr5EpWsBMjs/je8dlCoBt2Zh1/fjUkxoSpOt shggm2Mg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dbCjJ-00041t-F7; Fri, 28 Jul 2017 21:23:29 +0000 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dbCi6-000309-2w; Fri, 28 Jul 2017 21:22:17 +0000 Received: by mail-wm0-x244.google.com with SMTP id r77so15674731wmd.2; Fri, 28 Jul 2017 14:21:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ps5mfA52f6Qmx0oApGWBjoZP9ga5SeXvyCvKl92Nas8=; b=X2PgOwAYVE/bkG0kQOcJG7vwy9jYnhA4uFiZjWk+eMb3zDBnoez52Wt59iMhANbk2I IF/f1DGJHW/fyGdoP749JiS4Q/UtMGMRKzoVu6DHo0QYiFa+Axdm8TyOR0aYmUqnzYmc RRajjaEjJdzej+OK2SoRqGuoCLTlArIkjmG78jUGg3t1i2aSFIekmMSEAa+YLzLGXY4h x1RW3foCisO2CQ5U3RzqRoQ4DEof8xVVGQnkI1JdwC4Sr6Cm0Th2lWIuUussB5teIrhA Nk7/CG8onkW3R2tiAH7hfljMDvRpHVMl2sUEHZ2j1xMVBtseRRHos7oISfR0V75MU947 u1oQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ps5mfA52f6Qmx0oApGWBjoZP9ga5SeXvyCvKl92Nas8=; b=hcstXhS43JdXvdfim/Hoe1qLvStAzJ3asdqKTL2a9rpZO5VYrfOXnwWtzaNmvP5fbf IPtsMdL6TKiz7LnV0TfXMLxxJ6Nxqoeu1egEzb4f9oOiY0mxJ/XXzqtlRK1gY77vA2eJ 6na3zA7yQ63hmaDKEfALh/cQ1+q5Dq9hZbbN9TRTa/qQQyGh0VuT4izx8KxsDwpu+6sQ oFjpGQXKsXJ+/O6eLkvXzc8ELJPRIGs/CJ8/fij1ef2bemxEEPd+X2OELM3cziaxxURf LzTk5awRGCgPvWWHZ+cshwqLPH36+LlbATQmWfcRz2XdJeWICfxy3+vhkm3kxfTSoy0P B/Kw== X-Gm-Message-State: AIVw112nITgkmG8cG8bORU+MqyZP93sTEWDQsDBgvxjBNIfJLeBhSJMf cGpCjD8AhbvhdJtjc80= X-Received: by 10.28.188.85 with SMTP id m82mr6215661wmf.3.1501276908518; Fri, 28 Jul 2017 14:21:48 -0700 (PDT) Received: from blackbox.darklights.net (p200300DCD3DFC504D5EDFADFEF0C8DD0.dip0.t-ipconnect.de. [2003:dc:d3df:c504:d5ed:fadf:ef0c:8dd0]) by smtp.googlemail.com with ESMTPSA id u62sm18070744wmd.5.2017.07.28.14.21.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 28 Jul 2017 14:21:47 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, khilman@baylibre.com, carlo@caione.org, linux@armlinux.org.uk, robh+dt@kernel.org Subject: [PATCH v5 2/6] ARM: smp_scu: add a helper for powering on a specific CPU Date: Fri, 28 Jul 2017 23:21:34 +0200 Message-Id: <20170728212138.12217-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170728212138.12217-1-martin.blumenstingl@googlemail.com> References: <20170728212138.12217-1-martin.blumenstingl@googlemail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170728_142214_631572_0923F3E2 X-CRM114-Status: GOOD ( 10.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, f.fainelli@gmail.com, Martin Blumenstingl , arnd@arndb.de MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP To boot the secondary CPUs on the Amlogic Meson8/Meson8m2 (Cortex-A9) and Meson8b (Cortex-A5) SoCs we have to enable SCU mode SCU_PM_NORMAL, otherwise the secondary cores will not start. This patch adds a scu_cpu_power_enable() function which can be used to enable SCU_PM_NORMAL for a specific (logical) CPU. An internal helper function is also created, to avoid code duplication with scu_power_mode(). Signed-off-by: Martin Blumenstingl --- arch/arm/include/asm/smp_scu.h | 6 ++++++ arch/arm/kernel/smp_scu.c | 39 +++++++++++++++++++++++++++++---------- 2 files changed, 35 insertions(+), 10 deletions(-) diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h index bfe163c40024..11e636f33ed9 100644 --- a/arch/arm/include/asm/smp_scu.h +++ b/arch/arm/include/asm/smp_scu.h @@ -26,6 +26,7 @@ static inline unsigned long scu_a9_get_base(void) #ifdef CONFIG_HAVE_ARM_SCU unsigned int scu_get_core_count(void __iomem *); int scu_power_mode(void __iomem *, unsigned int); +int scu_cpu_power_enable(void __iomem *, unsigned int); #else static inline unsigned int scu_get_core_count(void __iomem *scu_base) { @@ -35,6 +36,11 @@ static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode) { return -EINVAL; } +static inline int scu_cpu_power_enable(void __iomem *scu_base, + unsigned int mode) +{ + return -EINVAL; +} #endif #if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU) diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c index 72f9241ad5db..ef09121b18eb 100644 --- a/arch/arm/kernel/smp_scu.c +++ b/arch/arm/kernel/smp_scu.c @@ -72,18 +72,12 @@ void scu_enable(void __iomem *scu_base) } #endif -/* - * Set the executing CPUs power mode as defined. This will be in - * preparation for it executing a WFI instruction. - * - * This function must be called with preemption disabled, and as it - * has the side effect of disabling coherency, caches must have been - * flushed. Interrupts must also have been disabled. - */ -int scu_power_mode(void __iomem *scu_base, unsigned int mode) +static int scu_set_power_mode_internal(void __iomem *scu_base, + unsigned int logical_cpu, + unsigned int mode) { unsigned int val; - int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); + int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0); if (mode > 3 || mode == 1 || cpu > 3) return -EINVAL; @@ -94,3 +88,28 @@ int scu_power_mode(void __iomem *scu_base, unsigned int mode) return 0; } + +/* + * Set the executing CPUs power mode as defined. This will be in + * preparation for it executing a WFI instruction. + * + * This function must be called with preemption disabled, and as it + * has the side effect of disabling coherency, caches must have been + * flushed. Interrupts must also have been disabled. + */ +int scu_power_mode(void __iomem *scu_base, unsigned int mode) +{ + return scu_set_power_mode_internal(scu_base, smp_processor_id(), mode); +} + +/* + * Set the executing CPUs power mode to SCU_PM_NORMAL. + * + * This function must be called with preemption disabled, and as it + * has the side effect of disabling coherency, caches must have been + * flushed. Interrupts must also have been disabled. + */ +int scu_cpu_power_enable(void __iomem *scu_base, unsigned int cpu) +{ + return scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL); +}