From patchwork Thu Aug 3 15:15:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 9879321 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4D52A60360 for ; Thu, 3 Aug 2017 15:18:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3F5CD28946 for ; Thu, 3 Aug 2017 15:18:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 346A328948; Thu, 3 Aug 2017 15:18:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AD53B28946 for ; Thu, 3 Aug 2017 15:18:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=Cn0dtytCAWT2NhC3qEes5DwtchARiB+YDmeVtxljtPQ=; b=ZluG2JMKYgfxR1Vp84SQ5iPunk tpHYtMzovZ+be3syLFmQpXMtldTJWZM29cNhPPRlYAjW8xJJlg7LV7Tm/85q8kG4tPPRzaRn3nayp 3Ldk8afUsrrm3wHH76jCl+yy645ZkHnzMZ4WvKUJeMh8Wu3oZ9PJsRSFn/itnuIWJis8JOf47VF1u r59Ht9fWuQLnFOqKTtVfOOLXgzH+r5O3fkhAvuHxBagp1RXkwx+O9WPXFQ/oPrjE5iPN42H2TELZz 1opvN26R3IF3gwoETP78HxqKxwrFgXO2W3CjSFiMto+R5y3B9VGqw/4Bl79t7pJyc3/BR8aP/PEej wyA1vgkQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1ddHtR-00082c-BS; Thu, 03 Aug 2017 15:18:33 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1ddHs9-0006tX-5V for linux-arm-kernel@lists.infradead.org; Thu, 03 Aug 2017 15:17:17 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 858BF15BF; Thu, 3 Aug 2017 08:16:55 -0700 (PDT) Received: from melchizedek.cambridge.arm.com (melchizedek.cambridge.arm.com [10.1.207.55]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 29AEB3F540; Thu, 3 Aug 2017 08:16:54 -0700 (PDT) From: James Morse To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/3] arm64: entry: Exceptions from single-step should leave debug masked Date: Thu, 3 Aug 2017 16:15:33 +0100 Message-Id: <20170803151533.29438-4-james.morse@arm.com> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170803151533.29438-1-james.morse@arm.com> References: <20170803151533.29438-1-james.morse@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170803_081713_322026_E3BBADB7 X-CRM114-Status: GOOD ( 10.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Pratyush Anand , Catalin Marinas , Will Deacon , AKASHI Takahiro , James Morse MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP If we interrupted an instruction being single-stepped we may end up taking a single-step exception from the interrupt handler. This confuses single-step users who are typically just waiting for 'the next' single step exception before re-enabling {break,watch}points. Returning from the interrupt causes us to hit the {break,watch}point again. For the least-surprising results, lets confine single-step to its intended context. From the ARM-ARM DDI 0487B.a, D.12.5 'Behaviour in the active-not-pending state's 'If the PE takes an exception' section, we enter the inactive state because the exception sets PSTATE.D. D2.12.6 'Entering the active-pending state', from the inactive state, we re-enter active-pending if we clear PSTATE.D. This causes a debug single step exception and we we step the exception handler. Change the EL1 entry.S handlers to inherit their debug state if the SPSR.SS bit is clear, instead of unconditionally unmasking it. This bit will be set if we took this exception instead of stepping an instruction. This isn't needed for the EL0 entry.S handlers as we will have cleared MDSCR_EL1.SS on entry from EL0. Signed-off-by: James Morse CC: Pratyush Anand CC: AKASHI Takahiro --- arch/arm64/include/asm/assembler.h | 14 ++++++++++++++ arch/arm64/kernel/entry.S | 10 +++++----- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 1c490c578a2e..96f01cc33d0e 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -25,6 +25,7 @@ #include #include +#include #include #include #include @@ -66,6 +67,19 @@ msr daifclr, #8 .endm + /* + * If we interrupted single step from EL1 then we may end up stepping + * the exception handler. Leave debug masked. Otherwise inherit + * the value we interrupted. + */ + .macro inherit_dbg, pstate, reg + mov_q \reg, (PSR_D_BIT | DBG_SPSR_SS) + and \reg, \reg, \pstate + cbnz \reg, 9998f + enable_dbg +9998: + .endm + .macro disable_step_tsk, flgs, tmp tbz \flgs, #TIF_SINGLESTEP, 9990f mrs \tmp, mdscr_el1 diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index eed2d51e16e6..9788bb47a7f7 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -431,7 +431,7 @@ el1_da: * Data abort handling */ mrs x3, far_el1 - enable_dbg + inherit_dbg, pstate=x23 reg=x0 // re-enable interrupts if they were enabled in the aborted context tbnz x23, #7, 1f // PSR_I_BIT enable_irq @@ -446,14 +446,14 @@ el1_sp_pc: * Stack or PC alignment exception handling */ mrs x0, far_el1 - enable_dbg + inherit_dbg, pstate=x23 reg=x2 mov x2, sp b do_sp_pc_abort el1_undef: /* * Undefined instruction */ - enable_dbg + inherit_dbg, pstate=x23 reg=x0 mov x0, sp b do_undefinstr el1_dbg: @@ -469,7 +469,7 @@ el1_dbg: kernel_exit 1 el1_inv: // TODO: add support for undefined instructions in kernel mode - enable_dbg + inherit_dbg, pstate=x23 reg=x0 mov x0, sp mov x2, x1 mov x1, #BAD_SYNC @@ -479,7 +479,7 @@ ENDPROC(el1_sync) .align 6 el1_irq: kernel_entry 1 - enable_dbg + inherit_dbg, pstate=x23 reg=x0 #ifdef CONFIG_TRACE_IRQFLAGS bl trace_hardirqs_off #endif