From patchwork Mon Aug 28 12:16:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 9925383 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5AC7C60329 for ; Mon, 28 Aug 2017 12:18:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4D02F284C4 for ; Mon, 28 Aug 2017 12:18:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 41A4628694; Mon, 28 Aug 2017 12:18:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, RCVD_IN_DNSWL_LOW, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BDC61284C4 for ; Mon, 28 Aug 2017 12:18:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=Crz/d3j7vZ1J6kqhIZG+VTZCrjlZJUbRGubVLFQnF3U=; b=k7bUOhwEcSgxh+vjd4P5F/uRjO dK8wLuOyDI3uYar2+bKu1EsB5iZN2oVzT5KYnV/2QD2zFMbQBBlvyFVNTqwpARBawd5w8K3VVhUNH 1VBOQEvgSlAfdQRqxz/auTKMNOe4xBW41Xu2EN6c20TojDA7kixA62ACwqIdhmSkRRvkO2tV7uErb 4kzHaqEd5sDEn9reIQKAKaRYdRE9ptia1VzbWZi7s7ep6voYOyrdphoiRTAfhNq+4piub8IUQte9t LL5MlMZceXP17WEvoFVyQYEB6OKbCP7YbWqUV+lTIwW131vpJJlKjS+kP64M17s71rTw64vYanjXK MhOVpAIw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dmIzl-0007Pz-BU; Mon, 28 Aug 2017 12:18:21 +0000 Received: from bhuna.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e3e3]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dmIy9-00061a-Tf; Mon, 28 Aug 2017 12:17:09 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: rperier) with ESMTPSA id B3B6D26C8F9 From: Romain Perier To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Heiko Stuebner , Srinivas Kandagatla Subject: [PATCH 3/4] nvmem: rockchip: add support for RK3368 Date: Mon, 28 Aug 2017 14:16:03 +0200 Message-Id: <20170828121604.15968-4-romain.perier@collabora.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170828121604.15968-1-romain.perier@collabora.com> References: <20170828121604.15968-1-romain.perier@collabora.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170828_051706_980556_5470F0B1 X-CRM114-Status: GOOD ( 11.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Pawel Moll , Ian Campbell , linux-rockchip@lists.infradead.org, Rob Herring , Kumar Gala , Romain Perier , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This adds the necessary functions and data for handling support on RK3368 SoCs. Signed-off-by: Romain Perier Acked-by: Rob Herring --- .../devicetree/bindings/nvmem/rockchip-efuse.txt | 1 + drivers/nvmem/rockchip-efuse.c | 80 ++++++++++++++++++++++ 2 files changed, 81 insertions(+) diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt index 1ff02afdc55a..60bec4782806 100644 --- a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt +++ b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt @@ -6,6 +6,7 @@ Required properties: - "rockchip,rk3188-efuse" - for RK3188 SoCs. - "rockchip,rk3228-efuse" - for RK3228 SoCs. - "rockchip,rk3288-efuse" - for RK3288 SoCs. + - "rockchip,rk3368-efuse" - for RK3368 SoCs. - "rockchip,rk3399-efuse" - for RK3399 SoCs. - reg: Should contain the registers location and exact eFuse size - clocks: Should be the clock id of eFuse diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c index 63e3eb55f3ac..4e11f251035f 100644 --- a/drivers/nvmem/rockchip-efuse.c +++ b/drivers/nvmem/rockchip-efuse.c @@ -14,6 +14,7 @@ * more details. */ +#include #include #include #include @@ -46,9 +47,17 @@ #define REG_EFUSE_CTRL 0x0000 #define REG_EFUSE_DOUT 0x0004 +/* SMC function IDs for SiP Service queries */ +#define ROCKCHIP_SIP_ACCESS_REG 0x82000002 + +/* SIP access registers: read or write */ +#define ROCKCHIP_SIP_SECURE_REG_RD 0x0 +#define ROCKCHIP_SIP_SECURE_REG_WR 0x1 + struct rockchip_efuse_chip { struct device *dev; void __iomem *base; + phys_addr_t phys; struct clk *clk; }; @@ -92,6 +101,72 @@ static int rockchip_rk3288_efuse_read(void *context, unsigned int offset, return 0; } +static u32 smc_reg_read(u32 addr_phy) +{ + struct arm_smccc_res res; + + arm_smccc_smc(ROCKCHIP_SIP_ACCESS_REG, 0, addr_phy, + ROCKCHIP_SIP_SECURE_REG_RD, 0, 0, 0, 0, &res); + if (res.a0) + pr_err("%s error: %d, addr phy: 0x%x\n", __func__, (int)res.a0, + addr_phy); + return res.a1; +} + +static u32 smc_reg_write(u32 addr_phy, u32 val) +{ + struct arm_smccc_res res; + + arm_smccc_smc(ROCKCHIP_SIP_ACCESS_REG, val, addr_phy, + ROCKCHIP_SIP_SECURE_REG_WR, 0, 0, 0, 0, &res); + if (res.a0) + pr_err("%s error: %d, addr phy: 0x%x\n", __func__, (int)res.a0, + addr_phy); + return res.a0; +} + +static int rockchip_rk3368_efuse_read(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct rockchip_efuse_chip *efuse = context; + u8 *buf = val; + int ret; + + ret = clk_prepare_enable(efuse->clk); + if (ret < 0) { + dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); + return ret; + } + + smc_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_LOAD | RK3288_PGENB); + udelay(1); + while (bytes--) { + smc_reg_write(efuse->phys + REG_EFUSE_CTRL, + smc_reg_read(efuse->phys + REG_EFUSE_CTRL) & + (~(RK3288_A_MASK << RK3288_A_SHIFT))); + smc_reg_write(efuse->phys + REG_EFUSE_CTRL, + smc_reg_read(efuse->phys + REG_EFUSE_CTRL) | + ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT)); + + udelay(1); + smc_reg_write(efuse->phys + REG_EFUSE_CTRL, + smc_reg_read(efuse->phys + REG_EFUSE_CTRL) | + RK3288_STROBE); + udelay(1); + *buf++ = smc_reg_read(efuse->phys + REG_EFUSE_DOUT); + smc_reg_write(efuse->phys + REG_EFUSE_CTRL, + smc_reg_read(efuse->phys + REG_EFUSE_CTRL) & + (~RK3288_STROBE)); + udelay(1); + } + + /* Switch to standby mode */ + smc_reg_write(efuse->phys + REG_EFUSE_CTRL, RK3288_PGENB | RK3288_CSB); + + clk_disable_unprepare(efuse->clk); + return 0; +} + static int rockchip_rk3399_efuse_read(void *context, unsigned int offset, void *val, size_t bytes) { @@ -178,6 +253,10 @@ static const struct of_device_id rockchip_efuse_match[] = { .data = (void *)&rockchip_rk3288_efuse_read, }, { + .compatible = "rockchip,rk3368-efuse", + .data = (void *)&rockchip_rk3368_efuse_read, + }, + { .compatible = "rockchip,rk3399-efuse", .data = (void *)&rockchip_rk3399_efuse_read, }, @@ -205,6 +284,7 @@ static int rockchip_efuse_probe(struct platform_device *pdev) return -ENOMEM; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + efuse->phys = res->start; efuse->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(efuse->base)) return PTR_ERR(efuse->base);