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[46.223.156.13]) by smtp.gmail.com with ESMTPSA id r14sm1600805wra.97.2017.09.08.01.10.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Sep 2017 01:10:53 -0700 (PDT) From: Jan Glauber To: Bjorn Helgaas Subject: [PATCH v4 2/3] PCI: Avoid bus reset for Cavium cn8xxx root ports Date: Fri, 8 Sep 2017 10:10:32 +0200 Message-Id: <20170908081033.3025-3-jglauber@cavium.com> X-Mailer: git-send-email 2.9.0.rc0.21.g7777322 In-Reply-To: <20170908081033.3025-1-jglauber@cavium.com> References: <20170908081033.3025-1-jglauber@cavium.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170908_011114_608469_64A5408F X-CRM114-Status: UNSURE ( 9.62 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kvm@vger.kernel.org, david.daney@cavium.com, linux-pci@vger.kernel.org, Jan Glauber , Robert Richter , linux-kernel@vger.kernel.org, Alex Williamson , Jon Masters , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: David Daney Root ports of cn8xxx do not function after bus reset when used with some e1000e and LSI HBA devices. Add a quirk to prevent bus reset on these root ports. Signed-off-by: David Daney [jglauber@cavium.com: fixed typo and whitespaces] Signed-off-by: Jan Glauber --- drivers/pci/quirks.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 140760403f36..2e4e7b6d1a79 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3364,6 +3364,14 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); +/* + * Root port on some Cavium CN8xxx chips do not successfully complete + * a bus reset when used with certain types of child devices. Config + * space access to the child may quit responding. Flag the root port + * as not supporting bus reset. + */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); + static void quirk_no_pm_reset(struct pci_dev *dev) { /*