| Message ID | 20170911155529.62891-3-icenowy@aosc.io (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Icenowy, On Tue, Sep 12, 2017 at 1:55 AM, Icenowy Zheng <icenowy@aosc.io> wrote: > The DE2 in H3/H5 has a clock control unit in it, and the behavior is > slightly different between H3 and H5. > > Add the common parts in H3/H5 DTSI, and add the compatible string in H3 > DTSI. > > The compatible string of H5 DE2 CCU will be added in a separated patch. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > arch/arm/boot/dts/sun8i-h3.dtsi | 4 ++++ > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 14 ++++++++++++++ > 2 files changed, 18 insertions(+) > > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > index 11240a8313c2..76a4cbc99bdb 100644 > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > @@ -85,6 +87,18 @@ > #size-cells = <1>; > ranges; > > + display_clocks: clock@1000000 { > + /* compatible is in per SoC .dtsi file */ I don't know device tree very well, but shouldn't this node be disabled so that it doesn't do anything weird on H5? Or are nodes without compatibles ignored? Thanks,
在 2017-09-11 23:55，Icenowy Zheng 写道： > The DE2 in H3/H5 has a clock control unit in it, and the behavior is > slightly different between H3 and H5. > > Add the common parts in H3/H5 DTSI, and add the compatible string in H3 > DTSI. > > The compatible string of H5 DE2 CCU will be added in a separated patch. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > arch/arm/boot/dts/sun8i-h3.dtsi | 4 ++++ > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 14 ++++++++++++++ > 2 files changed, 18 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi > b/arch/arm/boot/dts/sun8i-h3.dtsi > index b36f9f423c39..a8a1db79f362 100644 > --- a/arch/arm/boot/dts/sun8i-h3.dtsi > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > @@ -85,6 +85,10 @@ > compatible = "allwinner,sun8i-h3-ccu"; > }; > > +&display_clocks { > + compatible = "allwinner,sun8i-a83t-de2-clk"; Sorry, this compatible is wrong. Please wait for my new version of this patchset to add a allwinner,sun8i-h3-de2-clk and use it. (A83T doesn't have DE mod clk, but H3 has) > +}; > + > &mmc0 { > compatible = "allwinner,sun7i-a20-mmc"; > clocks = <&ccu CLK_BUS_MMC0>, > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > index 11240a8313c2..76a4cbc99bdb 100644 > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > @@ -40,9 +40,11 @@ > * OTHER DEALINGS IN THE SOFTWARE. > */ > > +#include <dt-bindings/clock/sun8i-de2.h> > #include <dt-bindings/clock/sun8i-h3-ccu.h> > #include <dt-bindings/clock/sun8i-r-ccu.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/reset/sun8i-de2.h> > #include <dt-bindings/reset/sun8i-h3-ccu.h> > #include <dt-bindings/reset/sun8i-r-ccu.h> > > @@ -85,6 +87,18 @@ > #size-cells = <1>; > ranges; > > + display_clocks: clock@1000000 { > + /* compatible is in per SoC .dtsi file */ > + reg = <0x01000000 0x100000>; > + clocks = <&ccu CLK_DE>, > + <&ccu CLK_BUS_DE>; > + clock-names = "mod", > + "bus"; > + resets = <&ccu RST_BUS_DE>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > syscon: syscon@1c00000 { > compatible = "allwinner,sun8i-h3-system-controller", > "syscon";
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..a8a1db79f362 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -85,6 +85,10 @@ compatible = "allwinner,sun8i-h3-ccu"; }; +&display_clocks { + compatible = "allwinner,sun8i-a83t-de2-clk"; +}; + &mmc0 { compatible = "allwinner,sun7i-a20-mmc"; clocks = <&ccu CLK_BUS_MMC0>, diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 11240a8313c2..76a4cbc99bdb 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -40,9 +40,11 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-h3-ccu.h> #include <dt-bindings/clock/sun8i-r-ccu.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/sun8i-de2.h> #include <dt-bindings/reset/sun8i-h3-ccu.h> #include <dt-bindings/reset/sun8i-r-ccu.h> @@ -85,6 +87,18 @@ #size-cells = <1>; ranges; + display_clocks: clock@1000000 { + /* compatible is in per SoC .dtsi file */ + reg = <0x01000000 0x100000>; + clocks = <&ccu CLK_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + syscon: syscon@1c00000 { compatible = "allwinner,sun8i-h3-system-controller", "syscon";
The DE2 in H3/H5 has a clock control unit in it, and the behavior is slightly different between H3 and H5. Add the common parts in H3/H5 DTSI, and add the compatible string in H3 DTSI. The compatible string of H5 DE2 CCU will be added in a separated patch. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- arch/arm/boot/dts/sun8i-h3.dtsi | 4 ++++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 14 ++++++++++++++ 2 files changed, 18 insertions(+)