From patchwork Sun Sep 17 03:19:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Br=C3=BCns?= X-Patchwork-Id: 9954573 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6CB4860352 for ; Sun, 17 Sep 2017 03:24:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5D19428B2C for ; Sun, 17 Sep 2017 03:24:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 51C7C28C37; Sun, 17 Sep 2017 03:24:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CAFB628BCA for ; Sun, 17 Sep 2017 03:24:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CiFwjDUfjUpYuszeiUguz9eWHAGfeMtRk4QtpkLrZ4Y=; b=r+hIVtulxxIcfR Zgdfir2tW2Jh2BB/qJVzRelC2udcDlyHxYw89pOrC6vN4HDFd8fszr3Zxr/sf8wobCHNOb0BHwXIg +uJdxRLV4yLIrrJRTXUfUXaMhe98/Pwgr+XIr/uXrBwhtsYZ9qQVlmil/K/3X3ztfyktGgnwQZgKy oYwtDCujmH8vIQaNfPHyNFzCkh3loFYzTZifdDRSq671yIvf2Jh51p2HOTiHDsOs9eciBT/xv3Tos Vlc5vd2Q1dEJ/n7Lqx6ZrvpIaA3y5PZYvEfNqCyQMmXFXwXJP43F/9BBLIEZyVeFUkN0GP/mJLJRx 5/va+qlBL+BvVzzNcU6w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dtQBN-0004Jd-05; Sun, 17 Sep 2017 03:23:45 +0000 Received: from mail-out-2.itc.rwth-aachen.de ([134.130.5.47]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dtQ8H-0001Rr-69 for linux-arm-kernel@lists.infradead.org; Sun, 17 Sep 2017 03:20:45 +0000 X-IronPort-AV: E=Sophos;i="5.42,405,1500933600"; d="scan'208";a="13727178" Received: from rwthex-w1-a.rwth-ad.de ([134.130.26.156]) by mail-in-2.itc.rwth-aachen.de with ESMTP; 17 Sep 2017 05:20:06 +0200 Received: from pebbles.fritz.box (85.183.223.53) by rwthex-w1-a.rwth-ad.de (2002:8682:1a9c::8682:1a9c) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1034.26; Sun, 17 Sep 2017 05:20:04 +0200 From: =?UTF-8?q?Stefan=20Br=C3=BCns?= To: Subject: [PATCH v2 02/10] dmaengine: sun6i: Correct burst length field offsets for H3 Date: Sun, 17 Sep 2017 05:19:48 +0200 Message-ID: <20170917031956.28010-3-stefan.bruens@rwth-aachen.de> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170917031956.28010-1-stefan.bruens@rwth-aachen.de> References: <20170917031956.28010-1-stefan.bruens@rwth-aachen.de> MIME-Version: 1.0 X-Originating-IP: [85.183.223.53] X-ClientProxiedBy: rwthex-w1-b.rwth-ad.de (2002:8682:1a9d::8682:1a9d) To rwthex-w1-a.rwth-ad.de (2002:8682:1a9c::8682:1a9c) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170916_202033_758358_D085C9E6 X-CRM114-Status: GOOD ( 10.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Vinod Koul , Andre Przywara , linux-kernel@vger.kernel.org, Code Kipper , Chen-Yu Tsai , Rob Herring , dmaengine@vger.kernel.org, Maxime Ripard , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP For the H3, the burst lengths field offsets in the channel configuration register differs from earlier SoC generations. Using the A31 register macros actually configured the H3 controller do to bursts of length 1 always, which although working leads to higher bus utilisation. Signed-off-by: Stefan Brüns Acked-by: Maxime Ripard --- drivers/dma/sun6i-dma.c | 36 +++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index 45bcd5271d94..a6fc066a0ac6 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -68,13 +68,15 @@ #define DMA_CHAN_CFG_SRC_DRQ(x) ((x) & 0x1f) #define DMA_CHAN_CFG_SRC_IO_MODE BIT(5) #define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5) -#define DMA_CHAN_CFG_SRC_BURST(x) (((x) & 0x3) << 7) +#define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7) +#define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6) #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9) #define DMA_CHAN_CFG_DST_DRQ(x) (DMA_CHAN_CFG_SRC_DRQ(x) << 16) #define DMA_CHAN_CFG_DST_IO_MODE (DMA_CHAN_CFG_SRC_IO_MODE << 16) #define DMA_CHAN_CFG_DST_LINEAR_MODE (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16) -#define DMA_CHAN_CFG_DST_BURST(x) (DMA_CHAN_CFG_SRC_BURST(x) << 16) +#define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16) +#define DMA_CHAN_CFG_DST_BURST_H3(x) (DMA_CHAN_CFG_SRC_BURST_H3(x) << 16) #define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16) #define DMA_CHAN_CUR_SRC 0x10 @@ -115,6 +117,7 @@ struct sun6i_dma_config { * BSP kernel source code. */ void (*clock_autogate_enable)(); + void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst); }; /* @@ -284,6 +287,18 @@ static void sun6i_enable_clock_autogate_h3(struct sun6i_dma_dev *sdev) writel(SUNXI_H3_DMA_GATE_ENABLE, sdev->base + SUNXI_H3_DMA_GATE); } +static void sun6i_set_burst_length_a31(u32 *p_cfg, s8 src_burst, s8 dst_burst) +{ + *p_cfg |= DMA_CHAN_CFG_SRC_BURST_A31(src_burst) | + DMA_CHAN_CFG_DST_BURST_A31(dst_burst); +} + +static void sun6i_set_burst_length_h3(u32 *p_cfg, s8 src_burst, s8 dst_burst) +{ + *p_cfg |= DMA_CHAN_CFG_SRC_BURST_H3(src_burst) | + DMA_CHAN_CFG_DST_BURST_H3(dst_burst); +} + static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan) { struct sun6i_desc *txd = pchan->desc; @@ -563,11 +578,11 @@ static int set_config(struct sun6i_dma_dev *sdev, if (dst_width < 0) return dst_width; - *p_cfg = DMA_CHAN_CFG_SRC_BURST(src_burst) | - DMA_CHAN_CFG_SRC_WIDTH(src_width) | - DMA_CHAN_CFG_DST_BURST(dst_burst) | + *p_cfg = DMA_CHAN_CFG_SRC_WIDTH(src_width) | DMA_CHAN_CFG_DST_WIDTH(dst_width); + sdev->cfg->set_burst_length(p_cfg, src_burst, dst_burst); + return 0; } @@ -610,11 +625,11 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | DMA_CHAN_CFG_DST_LINEAR_MODE | DMA_CHAN_CFG_SRC_LINEAR_MODE | - DMA_CHAN_CFG_SRC_BURST(burst) | DMA_CHAN_CFG_SRC_WIDTH(width) | - DMA_CHAN_CFG_DST_BURST(burst) | DMA_CHAN_CFG_DST_WIDTH(width); + sdev->cfg->set_burst_length(v_lli->cfg, burst, burst); + sun6i_dma_lli_add(NULL, v_lli, p_lli, txd); sun6i_dma_dump_lli(vchan, v_lli); @@ -1027,6 +1042,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = { .nr_max_requests = 30, .nr_max_vchans = 53, .clock_autogate_enable = sun6i_enable_clock_autogate_noop; + .set_burst_length = sun6i_set_burst_length_a31; }; /* @@ -1039,6 +1055,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = { .nr_max_requests = 24, .nr_max_vchans = 37, .clock_autogate_enable = sun6i_enable_clock_autogate_a23; + .set_burst_length = sun6i_set_burst_length_a31; }; static struct sun6i_dma_config sun8i_a83t_dma_cfg = { @@ -1046,13 +1063,12 @@ static struct sun6i_dma_config sun8i_a83t_dma_cfg = { .nr_max_requests = 28, .nr_max_vchans = 39, .clock_autogate_enable = sun6i_enable_clock_autogate_a23; + .set_burst_length = sun6i_set_burst_length_a31; }; /* * The H3 has 12 physical channels, a maximum DRQ port id of 27, * and a total of 34 usable source and destination endpoints. - * It also supports additional burst lengths and bus widths, - * and the burst length fields have different offsets. */ static struct sun6i_dma_config sun8i_h3_dma_cfg = { @@ -1060,6 +1076,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { .nr_max_requests = 27, .nr_max_vchans = 34, .clock_autogate_enable = sun6i_enable_clock_autogate_h3; + .set_burst_length = sun6i_set_burst_length_h3; }; /* @@ -1072,6 +1089,7 @@ static struct sun6i_dma_config sun8i_v3s_dma_cfg = { .nr_max_requests = 23, .nr_max_vchans = 24, .clock_autogate_enable = sun6i_enable_clock_autogate_a23; + .set_burst_length = sun6i_set_burst_length_a31; }; static const struct of_device_id sun6i_dma_match[] = {