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[82.243.161.21]) by smtp.googlemail.com with ESMTPSA id d9sm2789029wrd.37.2017.09.21.10.15.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Sep 2017 10:15:03 -0700 (PDT) From: Jerome Brunet To: Kevin Hilman , Carlo Caione Subject: [PATCH 5/7] ARM64: dts: meson-gxbb: adjust odroid-c2 gpio-line-names Date: Thu, 21 Sep 2017 19:14:48 +0200 Message-Id: <20170921171450.27407-6-jbrunet@baylibre.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170921171450.27407-1-jbrunet@baylibre.com> References: <20170921171450.27407-1-jbrunet@baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170921_101523_377573_FB9EE1D0 X-CRM114-Status: UNSURE ( 7.95 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Martin Blumenstingl , linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Jerome Brunet MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP GPIOX22 is now declared properly and TEST_N has been moved so the gpio-line-names of the odroid-c2 must be adjusted accordingly Signed-off-by: Jerome Brunet --- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index d147c853ab05..9fc50bc5f9f4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -194,7 +194,9 @@ "USB HUB nRESET", "USB OTG Power En", "J7 Header Pin2", "IR In", "J7 Header Pin4", "J7 Header Pin6", "J7 Header Pin5", "J7 Header Pin7", - "HDMI CEC", "SYS LED"; + "HDMI CEC", "SYS LED", + /* GPIO_TEST_N */ + ""; }; &pinctrl_periphs { @@ -233,11 +235,9 @@ "J2 Header Pin12", "J2 Header Pin13", "J2 Header Pin8", "J2 Header Pin10", "", "", "", "", "", - "J2 Header Pin11", "", "J2 Header Pin7", + "J2 Header Pin11", "", "J2 Header Pin7", "", /* Bank GPIOCLK */ - "", "", "", "", - /* GPIO_TEST_N */ - ""; + "", "", "", ""; }; &saradc {