From patchwork Tue Sep 26 22:23:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Al Stone X-Patchwork-Id: 9972805 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5A0AE6037E for ; Tue, 26 Sep 2017 22:34:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4DC0028BCD for ; Tue, 26 Sep 2017 22:34:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 42C4628FA6; Tue, 26 Sep 2017 22:34:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A325128BCD for ; Tue, 26 Sep 2017 22:34:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=8rt1sMsJYXgT8vOpiXbvD33UzeJS3YGrYQ3tNVeFR+o=; b=LDeF0K7f/zIs/TQpK75aeMP2px zCddc+43S42wZr9iD0rLMcVi/XKJUq7IDrM12IM5VoGjl4GXcCg3L4O/UIvkdBPhkdnDhX95MALmD P8o8pG26HGk2bEEd5WGcyMKT7AnOObWRYIb6UFTfGVwkHSHL+L2lpzWlOynIbyVevfXbu+39hsyfc jWUOlzzOna8OeNJGCcynOeLWTu2QQCLNhsavVNSQ32zi3Tnls/8JCX1s3LEE5hZAxN9oVMvK1GJY0 XfwaVEL4yWNKWCajxB8Mbvbtu7yEIbJVThf0hmADgBqUc/oUq9QmEU0iJm11UH9bfDw4M8s9tkbV0 4KcbWCmQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dwyQi-0000DY-Cd; Tue, 26 Sep 2017 22:34:16 +0000 Received: from mx1.redhat.com ([209.132.183.28]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dwyGo-0005oU-Kl for linux-arm-kernel@lists.infradead.org; Tue, 26 Sep 2017 22:24:06 +0000 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 755F968B5; Tue, 26 Sep 2017 22:23:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 755F968B5 Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=ahs3@redhat.com Received: from fidelio.ahs3 (ovpn-116-41.phx2.redhat.com [10.3.116.41]) by smtp.corp.redhat.com (Postfix) with ESMTP id 059A47AA5C; Tue, 26 Sep 2017 22:23:41 +0000 (UTC) From: Al Stone To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] arm64: cpuinfo: add human readable CPU names to /proc/cpuinfo Date: Tue, 26 Sep 2017 16:23:23 -0600 Message-Id: <20170926222324.17409-3-ahs3@redhat.com> In-Reply-To: <20170926222324.17409-1-ahs3@redhat.com> References: <20170926222324.17409-1-ahs3@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Tue, 26 Sep 2017 22:23:42 +0000 (UTC) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170926_152402_760714_D93B91BC X-CRM114-Status: GOOD ( 13.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Catalin Marinas , Will Deacon , Al Stone , Suzuki K Poulose MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP In the interest of making things easier for humans to use, add a "CPU name" line to /proc/cpuinfo for each CPU that uses plain old words instead of hex values. For example, instead of printing only CPU implementer 0x43 and CPU part 0x0A1, print also "CPU name : Cavium ThunderX". Note that this is not meant to be an exhaustive list of all possible implementers or CPUs (I'm not even sure that is knowable); this patch is intentionally limited to only those willing to provide info in arch/arm64/include/asm/cputype.h Signed-off-by: Al Stone Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose Cc: Mark Rutland --- arch/arm64/kernel/cpuinfo.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index e505007138eb..0b4261884862 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -75,6 +75,61 @@ static const char *const hwcap_str[] = { NULL }; +struct hw_part { + u16 id; + char *name; +}; + +static const struct hw_part arm_hw_part[] = { + { ARM_CPU_PART_AEM_V8, "AEMv8 Model" }, + { ARM_CPU_PART_FOUNDATION, "Foundation Model" }, + { ARM_CPU_PART_CORTEX_A57, "Cortex A57" }, + { ARM_CPU_PART_CORTEX_A53, "Cortex A53" }, + { ARM_CPU_PART_CORTEX_A73, "Cortex A73" }, + { (-1), "unknown" } /* Potenza == 0, unfortunately */ +}; + +static const struct hw_part apm_hw_part[] = { + { APM_CPU_PART_POTENZA, "Potenza" }, + { (-1), "unknown" } /* Potenza == 0, unfortunately */ +}; + +static const struct hw_part brcm_hw_part[] = { + { BRCM_CPU_PART_VULCAN, "Vulcan" }, + { (-1), "unknown" } /* Potenza == 0, unfortunately */ +}; + +static const struct hw_part cavium_hw_part[] = { + { CAVIUM_CPU_PART_THUNDERX, "ThunderX" }, + { CAVIUM_CPU_PART_THUNDERX_81XX, "ThunderX 81XX" }, + { CAVIUM_CPU_PART_THUNDERX_83XX, "ThunderX 83XX" }, + { (-1), "unknown" } /* Potenza == 0, unfortunately */ +}; + +static const struct hw_part qcom_hw_part[] = { + { QCOM_CPU_PART_FALKOR_V1, "Falkor v1" }, + { (-1), "unknown" } /* Potenza == 0, unfortunately */ +}; + +static const struct hw_part unknown_hw_part[] = { + { (-1), "unknown" } /* Potenza == 0, unfortunately */ +}; + +struct hw_impl { + u8 id; + const struct hw_part *parts; + char *name; +}; + +static const struct hw_impl hw_implementer[] = { + { ARM_CPU_IMP_ARM, arm_hw_part, "ARM Ltd." }, + { ARM_CPU_IMP_APM, apm_hw_part, "Applied Micro" }, + { ARM_CPU_IMP_CAVIUM, cavium_hw_part, "Cavium" }, + { ARM_CPU_IMP_BRCM, brcm_hw_part, "Broadcom" }, + { ARM_CPU_IMP_QCOM, qcom_hw_part, "Qualcomm" }, + { 0, unknown_hw_part, "unknown" } +}; + #ifdef CONFIG_COMPAT static const char *const compat_hwcap_str[] = { "swp", @@ -116,6 +171,9 @@ static int c_show(struct seq_file *m, void *v) { int i, j; bool compat = personality(current->personality) == PER_LINUX32; + u8 impl; + u16 part; + const struct hw_part *parts; for_each_online_cpu(i) { struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); @@ -132,6 +190,32 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n", MIDR_REVISION(midr), COMPAT_ELF_PLATFORM); + impl = (u8) MIDR_IMPLEMENTOR(midr); + for (j = 0; hw_implementer[j].id != 0; j++) { + if (hw_implementer[j].id == impl) { + seq_printf(m, "CPU name\t: %s ", + hw_implementer[j].name); + parts = hw_implementer[j].parts; + break; + } + } + if (hw_implementer[j].id == 0) { + seq_printf(m, "CPU name\t: %s ", + hw_implementer[j].name); + parts = hw_implementer[j].parts; + } + + part = (u16) MIDR_PARTNUM(midr); + for (j = 0; parts[j].id != (-1); j++) { + if (parts[j].id == part) { + seq_printf(m, "%s\n", parts[j].name); + break; + } + } + if (parts[j].id == (-1)) + seq_printf(m, "%s", parts[j].name); + seq_puts(m, "\n"); + seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", loops_per_jiffy / (500000UL/HZ), loops_per_jiffy / (5000UL/HZ) % 100);