From patchwork Wed Sep 27 13:32:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 9974101 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 09EA96037F for ; Wed, 27 Sep 2017 13:35:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EAB90284C4 for ; Wed, 27 Sep 2017 13:35:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DDD7828B82; Wed, 27 Sep 2017 13:35:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 68A23284C4 for ; Wed, 27 Sep 2017 13:35:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=uIBfPhY5uF7XoH1XybyVhYS5UEbawwOt4aNJwBWd1bU=; b=WT9Jp1+apP9pGE PNJG4bDaaD0DDMnst1ya3qEcI8hXCpZ005xJ6w00uY59/svLTLUKe+GKDpr/tzX5YtNsshwenGlgx Vi+3DQTzrIL07XEAUTEXBFezB9JuNi5C4Bf4XqZuYnK7ipyq94XENl8vKWMJ3/uCEHXtGyb5ZkyuY WpvRvKumre3XKl4ebwPQB35O4VnkjO1Tzv/41GbBdUNs5udRo3b0zEaIrVuK9a85jaX1lRA/t3kKU clMmjwvDZzpm9XCb00fbbHp8h2vTjRsR9ZwsMXmi/8DsVNaGO0AmhFq3dbsHhRU8M0MTXZbKGRTXi J80+V/+Do+32fw4cJ+fg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dxCV0-00028V-2H; Wed, 27 Sep 2017 13:35:38 +0000 Received: from szxga04-in.huawei.com ([45.249.212.190]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dxCUw-0001JZ-Bc for linux-arm-kernel@lists.infradead.org; Wed, 27 Sep 2017 13:35:36 +0000 Received: from 172.30.72.58 (EHLO DGGEMS401-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DIB16842; Wed, 27 Sep 2017 21:35:06 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.301.0; Wed, 27 Sep 2017 21:34:58 +0800 From: Shameer Kolothum To: , , , , , , , Subject: [PATCH v8 1/5] Doc: iommu/arm-smmu-v3: Add workaround for HiSilicon erratum 161010801 Date: Wed, 27 Sep 2017 14:32:37 +0100 Message-ID: <20170927133241.21036-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170927133241.21036-1-shameerali.kolothum.thodi@huawei.com> References: <20170927133241.21036-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.59CBA90A.015A, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 1199e1a103f72e2595b31297b988f396 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170927_063534_729768_5728AD03 X-CRM114-Status: GOOD ( 10.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, gabriele.paoloni@huawei.com, john.garry@huawei.com, linuxarm@huawei.com, Shameer Kolothum , linux-acpi@vger.kernel.org, iommu@lists.linux-foundation.org, wangzhou1@hisilicon.com, guohanjun@huawei.com, linux-arm-kernel@lists.infradead.org, devel@acpica.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: John Garry The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms hip06/hip07 to support the SMMU mappings for MSI transactions. On these platforms, GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch adds a compatible string to implement this errata for HiSilicon Hi161x SMMUv3 model on hip06/hip07 platforms. Also, the arm64 silicon errata is updated with this same erratum. Signed-off-by: John Garry [Shameer: Modified to use compatible string for errata] Signed-off-by: Shameer Kolothum Acked-by: Rob Herring --- Documentation/arm64/silicon-errata.txt | 1 + Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 66e8ce1..02816b1 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -70,6 +70,7 @@ stable kernels. | | | | | | Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 | | Hisilicon | Hip0{6,7} | #161010701 | N/A | +| Hisilicon | Hip0{6,7} | #161010801 | N/A | | | | | | | Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | | Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt index c9abbf3..3b0d599 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt @@ -7,11 +7,18 @@ the PCIe specification. ** SMMUv3 required properties: -- compatible : Should include: +- compatible : Should be one of: + + "arm,smmu-v3" + "hisilicon,hi161x-smmu-v3" + + depending on the particular implementation. * "arm,smmu-v3" for any SMMUv3 compliant implementation. This entry should be last in the compatible list. + * "hisilicon,hi161x-smmu-v3" for HiSilicon hi161x + SMMUv3 implementation on hip06/hip07 platforms. - reg : Base address and size of the SMMU.