From patchwork Wed Sep 27 13:32:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 9974109 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id ADF086037F for ; Wed, 27 Sep 2017 13:39:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9B66828D43 for ; Wed, 27 Sep 2017 13:39:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8E87728DF8; Wed, 27 Sep 2017 13:39:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 93CA828D43 for ; Wed, 27 Sep 2017 13:39:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WTqSPOv8p+IYftfzn4h7/lQrv6Gp3SfSnrdxGMzvvYQ=; b=ExwTr+83jRoRj+ REBHV9S7VDAOsVTflUvM2N1jSR4f9n5Uo2rD1ldUVS01/ru6iLNB6raWQ1ARTlhTdza/nsX4Hjsiq GTS7TaFhk9UTwcAryTJW6iXdGXNKp1qMJwPvJ3rD1STzbIIzioEicf26M8q0Bi1mRS9X4HStK6ggE +iPFGXoyEdtLq6wWSGZUktgrnVSQyujCIuaAq/m1QKHNFrbW2a+WMxeznINRaqaL0fhxiUWgrRUBo q9r8prN91Z3woUxTYS/SnE19O4pN/3uc+fR6C1oS3mdYMJoiUflrGgFMeL1RHeleq4TqdWkrV3+hT +IFP5R+F0yF25KaBKf0Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dxCXR-0004lY-4S; Wed, 27 Sep 2017 13:38:09 +0000 Received: from szxga04-in.huawei.com ([45.249.212.190]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dxCVC-0001we-3y for linux-arm-kernel@lists.infradead.org; Wed, 27 Sep 2017 13:36:04 +0000 Received: from 172.30.72.60 (EHLO DGGEMS401-HUB.china.huawei.com) ([172.30.72.60]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DIB16880; Wed, 27 Sep 2017 21:35:26 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.301.0; Wed, 27 Sep 2017 21:35:19 +0800 From: Shameer Kolothum To: , , , , , , , Subject: [PATCH v8 5/5] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Date: Wed, 27 Sep 2017 14:32:41 +0100 Message-ID: <20170927133241.21036-6-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170927133241.21036-1-shameerali.kolothum.thodi@huawei.com> References: <20170927133241.21036-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.59CBA91E.014B, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 13930aa6bc8fa600b0b18dc8ba8d5de5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170927_063552_349672_81B21797 X-CRM114-Status: GOOD ( 14.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, gabriele.paoloni@huawei.com, john.garry@huawei.com, linuxarm@huawei.com, Shameer Kolothum , linux-acpi@vger.kernel.org, iommu@lists.linux-foundation.org, wangzhou1@hisilicon.com, guohanjun@huawei.com, linux-arm-kernel@lists.infradead.org, devel@acpica.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. Signed-off-by: Shameer Kolothum --- drivers/iommu/arm-smmu-v3.c | 41 +++++++++++++++++++++++++++++++++++------ 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index e67ba6c..fb7f08d 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -413,6 +413,9 @@ #define MSI_IOVA_BASE 0x8000000 #define MSI_IOVA_LENGTH 0x100000 +#define SMMU_V3_GENERIC_ARM 0x0 +#define SMMU_V3_HISILICON_HI161X 0x1 + /* Until ACPICA headers cover IORT rev. C */ #ifndef ACPI_IORT_SMMU_HISILICON_HI161X #define ACPI_IORT_SMMU_HISILICON_HI161X 0x1 @@ -608,6 +611,7 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) #define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) +#define ARM_SMMU_OPT_RESV_HW_MSI (1 << 2) u32 options; struct arm_smmu_cmdq cmdq; @@ -696,6 +700,8 @@ static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) static void parse_driver_options(struct arm_smmu_device *smmu) { int i = 0; + const void *data = of_device_get_match_data(smmu->dev); + u32 model = *(u32 *)&data; do { if (of_property_read_bool(smmu->dev->of_node, @@ -705,6 +711,11 @@ static void parse_driver_options(struct arm_smmu_device *smmu) arm_smmu_options[i].prop); } } while (arm_smmu_options[++i].opt); + + if (model == SMMU_V3_HISILICON_HI161X) { + smmu->options |= ARM_SMMU_OPT_RESV_HW_MSI; + dev_notice(smmu->dev, "\tenabling workaround for HiSilicon erratum 161010801\n"); + } } /* Low-level queue manipulation functions */ @@ -1934,14 +1945,29 @@ static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { struct iommu_resv_region *region; + struct arm_smmu_master_data *master = dev->iommu_fwspec->iommu_priv; + struct arm_smmu_device *smmu = master->smmu; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + int resv = 0; - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI); - if (!region) - return; + if ((smmu->options & ARM_SMMU_OPT_RESV_HW_MSI)) { - list_add_tail(®ion->list, head); + resv = iommu_dma_get_msi_resv_regions(dev, head); + + if (resv < 0) { + dev_warn(dev, "HW MSI region resv failed: %d\n", resv); + return; + } + } + + if (!resv) { + region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, + prot, IOMMU_RESV_SW_MSI); + if (!region) + return; + + list_add_tail(®ion->list, head); + } iommu_dma_get_resv_regions(dev, head); } @@ -2667,6 +2693,7 @@ static void acpi_smmu_get_options(u32 model, struct arm_smmu_device *smmu) break; case ACPI_IORT_SMMU_HISILICON_HI161X: smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; + smmu->options |= ARM_SMMU_OPT_RESV_HW_MSI; break; } @@ -2862,7 +2889,9 @@ static void arm_smmu_device_shutdown(struct platform_device *pdev) } static const struct of_device_id arm_smmu_of_match[] = { - { .compatible = "arm,smmu-v3", }, + { .compatible = "hisilicon,hi161x-smmu-v3", + .data = (void *)SMMU_V3_HISILICON_HI161X }, + { .compatible = "arm,smmu-v3", .data = (void *)SMMU_V3_GENERIC_ARM }, { }, }; MODULE_DEVICE_TABLE(of, arm_smmu_of_match);