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Tue, 24 Oct 2017 12:55:38 -0700 (PDT) From: Doug Berger To: Gregory Fong Subject: [PATCH v2 1/7] gpio: brcmstb: Do not use gc->pin2mask() Date: Tue, 24 Oct 2017 12:54:45 -0700 Message-Id: <20171024195451.30535-2-opendmb@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171024195451.30535-1-opendmb@gmail.com> References: <20171024195451.30535-1-opendmb@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171024_125600_499701_A2DA80ED X-CRM114-Status: GOOD ( 12.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Florian Fainelli , Linus Walleij , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, Brian Norris , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Linus Walleij The pin2mask() accessor only shuffles BIT ORDER in big endian systems, i.e. the bitstuffing is swizzled big endian so "bit 0" is bit 7 or bit 15 or bit 31 or so. The brcmstb only uses big endian BYTE ORDER which will be taken car of by the ->write_reg() callback. Just use BIT(offset) to assign the bit. Cc: Gregory Fong Cc: Florian Fainelli Signed-off-by: Linus Walleij Reviewed-by: Florian Fainelli --- drivers/gpio/gpio-brcmstb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/gpio-brcmstb.c b/drivers/gpio/gpio-brcmstb.c index 27e92e57adae..9b8fcca7ad17 100644 --- a/drivers/gpio/gpio-brcmstb.c +++ b/drivers/gpio/gpio-brcmstb.c @@ -20,6 +20,7 @@ #include #include #include +#include #define GIO_BANK_SIZE 0x20 #define GIO_ODEN(bank) (((bank) * GIO_BANK_SIZE) + 0x00) @@ -68,16 +69,15 @@ static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, { struct gpio_chip *gc = &bank->gc; struct brcmstb_gpio_priv *priv = bank->parent_priv; - u32 mask = gc->pin2mask(gc, offset); u32 imask; unsigned long flags; spin_lock_irqsave(&gc->bgpio_lock, flags); imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id)); if (enable) - imask |= mask; + imask |= BIT(offset); else - imask &= ~mask; + imask &= ~BIT(offset); gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask); spin_unlock_irqrestore(&gc->bgpio_lock, flags); }